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Implement EFI capsule update functionality for PHYTEC K3-based SoMs. These SoMs feature various flash device options, including eMMC, OSPI NOR, and uSD card at the board level. This update provides the necessary logic to enable EFI capsule updates across all three flash devices, ensuring flexible and robust firmware upgrade capabilities. The GUID is dynamically generated for the board, to get it: efidebug capsule esrt ======================================== ESRT: fw_resource_count=3 ESRT: fw_resource_count_max=3 ESRT: fw_resource_version=1 [entry 0]============================== ESRT: fw_class=C7D64D6D-10B2-54BC-A3BF-06A9DC3653D9 ESRT: fw_type=unknown ESRT: fw_version=0 ESRT: lowest_supported_fw_version=0 ESRT: capsule_flags=0 ESRT: last_attempt_version=0 ESRT: last_attempt_status=success [entry 1]============================== ESRT: fw_class=09841C3F-F177-5D57-B1F6-754D92879205 ESRT: fw_type=unknown ESRT: fw_version=0 ESRT: lowest_supported_fw_version=0 ESRT: capsule_flags=0 ESRT: last_attempt_version=0 ESRT: last_attempt_status=success [entry 2]============================== ESRT: fw_class=D11A9016-515E-503A-8872-3FF65384D0C4 ESRT: fw_type=unknown ESRT: fw_version=0 ESRT: lowest_supported_fw_version=0 ESRT: capsule_flags=0 ESRT: last_attempt_version=0 ESRT: last_attempt_status=success ======================================== On the board (from uSD card containing capsule binaries at boot): load mmc 1:1 $loadaddr tiboot3-capsule.bin efidebug capsule update $loadaddr load mmc 1:1 $loadaddr tispl-capsule.bin efidebug capsule update $loadaddr load mmc 1:1 $loadaddr uboot-capsule.bin efidebug capsule update $loadaddr The binaries will be flashed to the flash device you are booted from. Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
19 lines
533 B
C
19 lines
533 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuration header file for PHYTEC phyCORE-AM64x kit
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*
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* Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
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* Author: Wadim Egorov <w.egorov@phytec.de>
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*/
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#ifndef __PHYCORE_AM64X_H
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#define __PHYCORE_AM64X_H
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/* DDR Configuration */
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#define CFG_SYS_SDRAM_BASE 0x80000000
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#define PHYCORE_AM6XX_FW_NAME_TIBOOT3 u"PHYCORE_AM64X_TIBOOT3"
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#define PHYCORE_AM6XX_FW_NAME_SPL u"PHYCORE_AM64X_SPL"
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#define PHYCORE_AM6XX_FW_NAME_UBOOT u"PHYCORE_AM64X_UBOOT"
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#endif /* __PHYCORE_AM64X_H */
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