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7a74e31938
Timer value is a 16 bits calculated from the wanted timeout and the
system clock. On powerpc/8xx, a timeout of 2s gives a value which
is over U16_MAX so U16_MAX shall be used. But the calculation is
casted to u16 so at the end the result is 63770 instead of 128906.
So the timer gets loaded with 63770 instead of 65535. It is not
a big difference in that case, but lets make the code correct and
cast to u32 instead of u16.
Fixes: 26e8ebcd7c ("watchdog: mpc8xxx: Make it generic")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 CS Systemes d'Information
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*/
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#include <env.h>
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#include <dm.h>
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#include <wdt.h>
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#include <clock_legacy.h>
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#include <asm/io.h>
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struct mpc8xxx_wdt {
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__be32 res0;
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__be32 swcrr; /* System watchdog control register */
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#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
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#define SWCRR_BME 0x00000080 /* Bus monitor enable (mpc8xx) */
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#define SWCRR_SWF 0x00000008 /* Software Watchdog Freeze (mpc8xx). */
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#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
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#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/
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#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
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__be32 swcnr; /* System watchdog count register */
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u8 res1[2];
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__be16 swsrr; /* System watchdog service register */
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u8 res2[0xf0];
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};
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struct mpc8xxx_wdt_priv {
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struct mpc8xxx_wdt __iomem *base;
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};
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static int mpc8xxx_wdt_reset(struct udevice *dev)
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{
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struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
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out_be16(&priv->base->swsrr, 0x556c); /* write magic1 */
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out_be16(&priv->base->swsrr, 0xaa39); /* write magic2 */
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return 0;
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}
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static int mpc8xxx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
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const char *mode = env_get("watchdog_mode");
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ulong prescaler = dev_get_driver_data(dev);
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u16 swtc = min_t(u32, timeout * get_board_sys_clk() / 1000 / prescaler, U16_MAX);
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u32 val;
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mpc8xxx_wdt_reset(dev);
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if (strcmp(mode, "off") == 0)
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val = (swtc << 16) | SWCRR_SWPR;
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else if (strcmp(mode, "nmi") == 0)
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val = (swtc << 16) | SWCRR_SWPR | SWCRR_SWEN;
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else
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val = (swtc << 16) | SWCRR_SWPR | SWCRR_SWEN | SWCRR_SWRI;
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if (IS_ENABLED(CONFIG_WDT_MPC8xxx_BME))
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val |= (CONFIG_WDT_MPC8xxx_BMT << 8) | SWCRR_BME;
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out_be32(&priv->base->swcrr, val);
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if (!(in_be32(&priv->base->swcrr) & SWCRR_SWEN))
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return -EBUSY;
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return 0;
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}
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static int mpc8xxx_wdt_stop(struct udevice *dev)
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{
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struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
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clrbits_be32(&priv->base->swcrr, SWCRR_SWEN);
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if (in_be32(&priv->base->swcrr) & SWCRR_SWEN)
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return -EBUSY;
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return 0;
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}
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static int mpc8xxx_wdt_of_to_plat(struct udevice *dev)
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{
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struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev);
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priv->base = (void __iomem *)devfdt_remap_addr(dev);
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if (!priv->base)
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return -EINVAL;
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return 0;
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}
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static const struct wdt_ops mpc8xxx_wdt_ops = {
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.start = mpc8xxx_wdt_start,
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.reset = mpc8xxx_wdt_reset,
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.stop = mpc8xxx_wdt_stop,
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};
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static const struct udevice_id mpc8xxx_wdt_ids[] = {
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{ .compatible = "fsl,pq1-wdt", .data = 0x800 },
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{ .compatible = "fsl,pq2pro-wdt", .data = 0x10000 },
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{}
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};
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U_BOOT_DRIVER(wdt_mpc8xxx) = {
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.name = "wdt_mpc8xxx",
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.id = UCLASS_WDT,
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.of_match = mpc8xxx_wdt_ids,
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.ops = &mpc8xxx_wdt_ops,
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.of_to_plat = mpc8xxx_wdt_of_to_plat,
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.priv_auto = sizeof(struct mpc8xxx_wdt_priv),
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};
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