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df831ebf61
The ADI SC598 includes a Designware QoS 5.20a IP block. This commit adds support for using the existing ethernet QoS driver with the SC598 SoC. Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com>
103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/**
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* (C) Copyright 2024 - Analog Devices, Inc.
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*
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* Written and/or maintained by Timesys Corporation
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*
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* Author: Greg Malysa <greg.malysa@timesys.com>
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* Additional Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
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*/
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#include <clk.h>
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#include <dm.h>
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#include <net.h>
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#include <phy.h>
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#include <reset.h>
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#include <linux/io.h>
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#include <asm/arch-adi/sc5xx/sc5xx.h>
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#include "dwc_eth_qos.h"
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static int eqos_start_resets_adi(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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/*
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* Settings need to latch with the DMA reset below. Currently only
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* rgmii is supported but other phy interfaces may be supported in
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* the future
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*/
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sc5xx_enable_rgmii();
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setbits_32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
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return 0;
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}
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static int eqos_probe_resources_adi(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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phy_interface_t interface;
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int ret;
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ret = eqos_get_base_addr_dt(dev);
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if (ret) {
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pr_err("eqos_get_base_addr_dt failed: %d\n", ret);
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return ret;
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}
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interface = eqos->config->interface(dev);
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if (interface == PHY_INTERFACE_MODE_NA) {
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pr_err("Invalid PHY interface\n");
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return -EINVAL;
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}
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return 0;
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}
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/**
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* rgmii tx clock rate is set to 125 MHz regardless of phy mode, and
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* by default the internal clock is always connected to 125 MHz. According
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* to the HRM it is invalid for this clock to have any other speed, so
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* the hardware won't work anyway if this is wrong.
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*/
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static ulong eqos_get_tick_clk_rate_adi(struct udevice *dev)
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{
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return 125 * 1000000;
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}
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static int eqos_get_enetaddr_adi(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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return eth_env_get_enetaddr("ethaddr", pdata->enetaddr);
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}
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static struct eqos_ops eqos_adi_ops = {
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.eqos_inval_desc = eqos_inval_desc_generic,
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.eqos_flush_desc = eqos_flush_desc_generic,
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.eqos_inval_buffer = eqos_inval_buffer_generic,
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.eqos_flush_buffer = eqos_flush_buffer_generic,
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.eqos_probe_resources = eqos_probe_resources_adi,
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.eqos_remove_resources = eqos_null_ops,
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.eqos_start_resets = eqos_start_resets_adi,
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.eqos_stop_resets = eqos_null_ops,
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.eqos_start_clks = eqos_null_ops,
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.eqos_stop_clks = eqos_null_ops,
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.eqos_calibrate_pads = eqos_null_ops,
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.eqos_disable_calibration = eqos_null_ops,
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.eqos_set_tx_clk_speed = eqos_null_ops,
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.eqos_get_enetaddr = eqos_get_enetaddr_adi,
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_adi,
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};
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struct eqos_config __maybe_unused eqos_adi_config = {
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.reg_access_always_ok = true,
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.mdio_wait = 20,
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.swr_wait = 50,
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.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
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.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_150_250,
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.axi_bus_width = EQOS_AXI_WIDTH_32,
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.interface = dev_read_phy_mode,
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.ops = &eqos_adi_ops,
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};
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