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44a26da8d9
Add support for loading the secure & non-secure pdi images and PL bitstream on the Versal Gen2 platform. The FPGA driver is enabled to load the bitstream in PDI format on the AMD Versal Gen2 device. PDI is the new programmable device image format for Versal Gen2, and the bitstream for the Versal Gen2 platform is generated exclusively in this format. With the enhanced SMC format in TF-A ensuring transparent payload forwarding for Versal Gen2, the u-boot driver must now handle the word swapping of PDI address that was previously done in TF-A for this API. The source code for the Versal2 loadpdi command and the CONFIG_CMD_VERSAL2 configuration has been removed. It now utilizes the fpga load <dev> <address> <length> command to load secure & non-secure pdi images. Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Link: https://lore.kernel.org/r/20250327105200.1262615-3-prasad.kummari@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
61 lines
1.4 KiB
C
61 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2019, Xilinx, Inc,
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* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
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*/
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#include <cpu_func.h>
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#include <log.h>
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#include <asm/arch/sys_proto.h>
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#include <memalign.h>
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#include <versalpl.h>
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#include <zynqmp_firmware.h>
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#include <asm/cache.h>
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static ulong versal_align_dma_buffer(ulong *buf, u32 len)
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{
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ulong *new_buf;
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if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
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new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
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memcpy(new_buf, buf, len);
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buf = new_buf;
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}
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return (ulong)buf;
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}
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static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
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bitstream_type bstype, int flags)
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{
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ulong bin_buf;
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int ret;
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u32 buf_lo, buf_hi;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
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debug("%s called!\n", __func__);
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flush_dcache_range(bin_buf, bin_buf + bsize);
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buf_lo = lower_32_bits(bin_buf);
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buf_hi = upper_32_bits(bin_buf);
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if (desc->family == xilinx_versal2) {
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ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_hi,
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buf_lo, 0, ret_payload);
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} else {
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ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
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buf_hi, 0, ret_payload);
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}
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if (ret)
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printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
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return ret;
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}
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struct xilinx_fpga_op versal_op = {
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.load = versal_load,
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};
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