mirror of
https://github.com/u-boot/u-boot.git
synced 2025-04-11 07:24:46 +00:00
39c9a94ea6
Change to use FIT and FIT_SIGNATURE when loading U-Boot proper in SPL to
allow checksum validation and fallback loading of FIT from a different
mmc device.
Checksum validation of FIT adds around 140 ms to boot time:
Before:
Mark Elapsed Stage
0 0 reset
13 13 TPL
6,957 6,944 end tpl
25,102 18,145 SPL
131,932 106,830 end phase
132,137 205 board_init_f
444,277 312,140 board_init_r
1,404,987 960,710 eth_common_init
1,519,110 114,123 eth_initialize
1,524,734 5,624 main_loop
1,525,452 718 cli_loop
After:
Mark Elapsed Stage
0 0 reset
13 13 TPL
6,957 6,944 end tpl
35,744 28,787 SPL
271,220 235,476 end phase
271,420 200 board_init_f
588,474 317,054 board_init_r
1,548,950 960,476 eth_common_init
1,663,105 114,155 eth_initialize
1,668,734 5,629 main_loop
1,669,417 683 cli_loop
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
101 lines
2.5 KiB
Text
101 lines
2.5 KiB
Text
CONFIG_ARM=y
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CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
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CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
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CONFIG_SYS_ARCH_TIMER=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_TEXT_BASE=0x01000000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SF_DEFAULT_SPEED=20000000
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CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-tinker-s"
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CONFIG_DM_RESET=y
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CONFIG_ROCKCHIP_RK3288=y
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CONFIG_TARGET_TINKER_RK3288=y
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_SYS_LOAD_ADDR=0x800800
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CONFIG_SPL_SIZE_LIMIT=0x4b000
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CONFIG_DEBUG_UART_BASE=0xff690000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_DEBUG_UART=y
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# CONFIG_ANDROID_BOOT_IMAGE is not set
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_FIT_SIGNATURE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_LEGACY_IMAGE_FORMAT=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-tinker-s.dtb"
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CONFIG_MISC_INIT_R=y
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CONFIG_SPL_PAD_TO=0x7f8000
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_BMP=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_PMIC=y
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CONFIG_CMD_REGULATOR=y
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# CONFIG_SPL_DOS_PARTITION is not set
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# CONFIG_SPL_EFI_PARTITION is not set
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_LIVE=y
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CONFIG_OF_UPSTREAM=y
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CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SYS_MMC_ENV_DEV=1
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_REGMAP=y
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CONFIG_SPL_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_SPL_SYSCON=y
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# CONFIG_SPL_SIMPLE_BUS is not set
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CONFIG_CLK=y
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CONFIG_SPL_CLK=y
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CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MISC=y
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CONFIG_ROCKCHIP_EFUSE=y
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CONFIG_I2C_EEPROM=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_PHY_REALTEK=y
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CONFIG_DM_ETH_PHY=y
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CONFIG_PHY_GIGE=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_PMIC=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_RAM=y
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CONFIG_SPL_RAM=y
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550_MEM32=y
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CONFIG_SYSRESET=y
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CONFIG_USB=y
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CONFIG_USB_DWC2=y
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CONFIG_ROCKCHIP_USB2_PHY=y
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CONFIG_USB_KEYBOARD=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_SMSC95XX=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_GADGET_DWC2_OTG=y
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CONFIG_VIDEO=y
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# CONFIG_VIDEO_BPP8 is not set
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CONFIG_DISPLAY=y
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CONFIG_VIDEO_ROCKCHIP=y
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CONFIG_DISPLAY_ROCKCHIP_HDMI=y
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CONFIG_CONSOLE_SCROLL_LINES=10
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CONFIG_CMD_DHRYSTONE=y
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CONFIG_SPL_CRC32=y
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CONFIG_ERRNO_STR=y
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