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Coreboot tables provide information about the CMOS-RAM checksum. Add a command which can check and update this. With this it is possible to adjust CMOS-RAM settings and tidy up the checksum afterwards. Signed-off-by: Simon Glass <sjg@chromium.org>
9 lines
288 B
Makefile
9 lines
288 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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obj-$(CONFIG_CMD_CBSYSINFO) += cbsysinfo.o
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obj-y += cpuid.o msr.o mtrr.o
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obj-$(CONFIG_CMD_CBCMOS) += cbcmos.o
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obj-$(CONFIG_CMD_EXCEPTION) += exception.o
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obj-$(CONFIG_USE_HOB) += hob.o
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obj-$(CONFIG_HAVE_FSP) += fsp.o
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obj-$(CONFIG_CMD_ZBOOT) += zboot.o
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