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37f85ab4ae
Use PMIC detection mechanism to find correct configuration. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
105 lines
2.7 KiB
C
105 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* T30 Grouper SPL stage configuration
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*
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* (C) Copyright 2010-2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* (C) Copyright 2022
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* Svyatoslav Ryhel <clamor95@gmail.com>
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*/
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#include <asm/gpio.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/tegra_i2c.h>
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#include <spl_gpio.h>
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#include <linux/delay.h>
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#define MAX77663_I2C_ADDR (0x3C << 1)
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#define MAX77663_REG_SD0 0x16
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#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0)
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#define MAX77663_REG_SD1 0x17
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#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1)
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#define MAX77663_REG_LDO4 0x2B
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#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4)
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#define MAX77663_REG_GPIO4 0x3A
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#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4)
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#define TPS65911_I2C_ADDR (0x2D << 1)
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#define TPS65911_VDDCTRL_OP_REG 0x28
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#define TPS65911_VDDCTRL_SR_REG 0x27
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#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
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#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
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#define TPS62361B_I2C_ADDR (0x60 << 1)
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#define TPS62361B_SET3_REG 0x03
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#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
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/*
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* PCB_ID[8] is GMI_CS2_N_PK3
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*
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* PMIC module detection
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* ==============================
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* PCB_ID[8] 0 1
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* PMIC Maxim TI
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*/
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static bool ti_pmic_detected(void)
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{
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/* Configure pinmux */
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pinmux_set_func(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_FUNC_GMI);
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pinmux_set_pullupdown(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_PULL_DOWN);
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pinmux_tristate_enable(PMUX_PINGRP_GMI_CS2_N_PK3);
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pinmux_set_io(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_PIN_INPUT);
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spl_gpio_input(NULL, TEGRA_GPIO(K, 3));
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return spl_gpio_get_value(NULL, TEGRA_GPIO(K, 3));
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}
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static void max_enable_cpu_vdd(void)
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{
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/* Set VDD_CORE to 1.200V. */
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tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA);
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udelay(1000);
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/* Bring up VDD_CPU to 1.0125V. */
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tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA);
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udelay(1000);
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/* Bring up VDD_RTC to 1.200V. */
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tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA);
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udelay(10 * 1000);
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/* Set 32k-out gpio state */
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tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA);
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}
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static void ti_enable_cpu_vdd(void)
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{
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/* Set VDD_CORE to 1.200V. */
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tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
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udelay(1000);
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/*
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* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
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* First set VDD to 1.0125V, then enable the VDD regulator.
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*/
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tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
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udelay(1000);
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tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
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udelay(10 * 1000);
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}
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void pmic_enable_cpu_vdd(void)
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{
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if (ti_pmic_detected())
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ti_enable_cpu_vdd();
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else
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max_enable_cpu_vdd();
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}
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