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https://github.com/u-boot/u-boot.git
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35638172f9
Initial creation of new system manager driver. Add supports for the SOCFPGA System Manager Register block which aggregates different peripheral function into one area. On 64 bit ARM parts, the system manager only can be accessed during EL3 mode, this driver model provide user the high level access to system register and abstract user from low level access. The base address of system manager can be retrieved using DT framework through the System Manager driver. Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
113 lines
2.8 KiB
C
113 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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*/
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/*
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* This driver supports the SOCFPGA System Manager Register block which
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* aggregates different peripheral function into one area.
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* On 64 bit ARM parts, the system manager only can be accessed during
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* EL3 mode. At lower exception level a SMC call is required to perform
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* the read and write operation.
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*/
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#define LOG_CATEGORY UCLASS_NOP
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#include <dm.h>
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#include <log.h>
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#include <misc.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/altera-sysmgr.h>
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#include <asm/arch/smc_api.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/intel-smc.h>
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static int altr_sysmgr_read_generic(struct udevice *dev, u32 *addr, u32 *value)
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{
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u64 args[1];
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u64 ret_arg;
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int ret = 0;
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debug("%s: %s(dev=%p, addr=0x%lx):\n", __func__,
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dev->name, dev, (uintptr_t)addr);
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if (current_el() == 3) {
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ret_arg = readl((uintptr_t)addr);
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} else {
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if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) {
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args[0] = (u64)(uintptr_t)addr;
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ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
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} else {
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pr_err("%s Failed to read system manager at lower privilege and without BL31\n",
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dev->name);
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return -EPROTONOSUPPORT;
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}
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}
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*value = (u32)ret_arg;
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return ret;
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}
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static int altr_sysmgr_write_generic(struct udevice *dev, u32 *addr, u32 value)
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{
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u64 args[2];
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int ret = 0;
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debug("%s: %s(dev=%p, addr=0x%lx, val=0x%x):\n", __func__,
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dev->name, dev, (uintptr_t)addr, value);
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if (current_el() == 3) {
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writel(value, (uintptr_t)addr);
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} else {
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if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) {
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args[0] = (u64)(uintptr_t)(addr);
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args[1] = value;
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ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
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} else {
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pr_err("%s Failed to write to system manager at lower privilege and without BL31\n",
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dev->name);
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return -EPROTONOSUPPORT;
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}
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}
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return ret;
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}
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static int altr_sysmgr_probe(struct udevice *dev)
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{
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fdt_addr_t addr;
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struct altr_sysmgr_priv *altr_priv = dev_get_priv(dev);
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debug("%s: %s(dev=%p):\n", __func__, dev->name, dev);
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE) {
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pr_err("%s dev_read_addr() failed\n", dev->name);
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return -ENODEV;
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}
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altr_priv->regs = (void __iomem *)addr;
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return 0;
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}
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static const struct altr_sysmgr_ops sysmgr_ops = {
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.read = altr_sysmgr_read_generic,
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.write = altr_sysmgr_write_generic,
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};
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static const struct udevice_id altr_sysmgr_ids[] = {
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{ .compatible = "altr,sys-mgr-s10" },
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{ .compatible = "altr,sys-mgr" },
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{ },
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};
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U_BOOT_DRIVER(altr_sysmgr) = {
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.name = "altr_sysmgr",
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.id = UCLASS_NOP,
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.of_match = altr_sysmgr_ids,
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.probe = altr_sysmgr_probe,
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.ops = &sysmgr_ops,
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.priv_auto = sizeof(struct altr_sysmgr_priv),
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.flags = DM_FLAG_PRE_RELOC,
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};
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