There is hard dependency for CLK_ZYNQMP to have zynqmp_pmufw_version()
but also FPGA code is calling this function which is possible to use
without actual CLK_ZYNQMP firmware driver to be enabled.
This patch enables the case where only fixed-clock CLK setup is used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This is a range of stackable network switches. The SoC is Armada-385 and
there are a number of variants with differing network port
configurations. The DP variants are intended for a harsher operating
environment so they use a different i2c mux and fit industrial-temp
parts.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The memory area [0x4000000-0x4200000[ is occupied by the PSCI firmware. Any
attempt to access it from U-Boot leads to an immediate crash.
So let's make the same memory reservation as the vendor device tree.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Use get_ram_size to determine if the RAM size on Turris Mox is 512 MiB
or 1 GiB.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
DTC issues a warning because #address-cells and #size-cells properties
are not set in the mdio node.
Also add ethernet1 alias.
Also add RTC node.
Also fix USB3 regulator startup delay time.
Also fix PCI Express SERDES speed to 5 GHz (this is only cosmetic, the
speed value is not used byt the comphy driver for PCI Express, but
should be 5 GHz nonetheless).
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Check if Mox modules are connected in supported mode, then configure
the MDIO addresses of switch modules.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Sync the Armada-38x device tree files with Linux 4.20-rc5. The changes
not taken are new compatible strings for the uart and nand flash
controller. The nand binding is best updated if/when the mtd/nand
infrastructure is updated.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
CLK and DM_RESET drivers are now available for all of
the Allwinner platforms, so enable them in arch/arm/Kconfig
Enabling CLK will select DM_RESET by default.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Update all A80 devicetree dtsi and dtsi files from
Linux-v4.18-rc3 with below commits.
arch/arm/boot/dts/sun9i-a80*:
commit 190e3138f9577885691540dca59c2f07540bde04
Merge: cafc87023b0d a7affb13b271
Author: Arnd Bergmann <arnd@arndb.de>
Date: Tue Mar 27 14:58:00 2018 +0200
Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
include/dt-bindings/*/sun9i-a80-*:
commit 783ab76ae553abc23f80ef7511052d055697531b
Author: Chen-Yu Tsai <wens@csie.org>
Date: Sat Jan 28 20:22:36 2017 +0800
clk: sunxi-ng: Add A80 Display Engine CCU
Note: sun9i-a80-cx-a99.dts is updated only uart0, since the same
dts is not available in Linux.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add common reset driver for all Allwinner SoC's.
Since CLK and RESET share common DT compatible, it is CLK driver
job is to bind the reset driver. So add CLK bind call on respective
SoC driver by passing ccu map descriptor so-that reset deassert,
deassert operations held based on ccu reset table defined from
CLK driver.
Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
since CLK and RESET share common DT compatible and code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT
module, DDR3 RAM and eMMC.
- add neutis-devboard target to dtb makefile
- add dtsi file for Neutis N5 needs
- add config file for Neutis N5 Dev board
Signed-off-by: Aleksandr Aleksandrov <aleksandr.aleksandrov@emlid.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: update proper commit head]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE.
However even the controller is enabled, the mux for the pins
are not set.
This patch follows the existing mux method. Since the pads are
different, separate check is added for each i2c.
Tested with A64-SOM204 board.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Remove aliases property name warning while compilation:
Warning (alias_paths): /aliases: aliases property name must
include only lowercase and '-'
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The ICIDs for the qdma device are not configured through SCFG but
through some registers found in the actual device register block.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
On LS1043A rev1.0 there are 4 interrupt pins for INTx, and on
rev1.1 there is only 1 for INTx, so the current fixup is inverse
of the fact.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
TFABOOT support includes:
- ls2088ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
- remove EL3 specific erratas for TFABOOT
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
TFABOOT support includes:
- ls1088ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- MC address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
- ifc chip select changes for TFABOOT
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Fixes for TFABOOT framework
- update eMMC bootsrc to SD_MMC
- Increase buffer size for mcinitcmd from 256 to 512
- Fix mcinitcmd and bootcmd for Secure Boot
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This fixes 'arch_lmb_reserve()' for ARM that tries to detect in which
DRAM bank 'sp' is in.
This code failed if a bank was at the end of physical address range
(i.e. size + length overflowed to 0).
To fix this, calculate 'bank_end' as 'size + length - 1' so that such
banks end at 0xffffffff, not 0.
Fixes: 15751403b6 ("ARM: bootm: don't assume sp is in DRAM bank 0")
Reported-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
This adds device tree for OMAP3 IGEP based boards and the DM_MMC driver.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add MMC nodes for HiKey board based on HI6220 SoC. There are three MMC
controllers in this SoC, first one used for eMMC, second one used
for SD card and third one is not used by u-boot.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
It enables DWC2 OTG gadget driver support for Poplar board. As
usb2_phy_init() is being always called from board_init(), we can save
the call from board_usb_init().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The SDMMC reset is missing from DT, so the reset manager cannot unreset
the SDMMC. Add the missing DT reset entry.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
OSC_27M_CLK should return 27MHz and OSC_32K_CLK should return
32768Hz to reflect the reality.
This also keeps the values in sync with the Linux clock tree.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
The CPU banner printed is as following:
CPU: CPU: Freescale i.MX8QXP RevB A35 at 147228 MHz
1. Drop the CPU:
2. Change vendor from Freescale to NXP
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The current value CTLUPD_AREF(0) is the reset value of the register,
so there is no need to write a value. If needed, the register can be
written using board specific CR settings.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
The CR80 register has multiple interrupt bits, the code is supposed
to check bit 8 but instead uses a logical and. In most cases this
probably did not affect real operations since at that stage typically
none of the other bits are set.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
According to the data sheet bits 10-8 are PHYDRAM_CK_EN. Fix mask
to allow setting PHYDRAM_CK_EN correctly.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
The Vybrid reference manual VFXXXRM Rev. 0 10/2016 states in chapter
5.2.6.1 DUMMY PADS (DDR/QuadSPI) that those pads need to be programed
for correct operation of DDR. Assume the default DDR pin configuration
which seems to work well on a Colibri VF50.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
When running usb dwc3 gadget driver, we meet random USB enumeration failure in fastboot.
The root cause is a cache coherence issue. When it happens, the ctrl_req in
gadget driver is allocated at 0xfe932f40, and the usb_composite_dev (cdev)
is allocated at 0xfe932f60. So after we submit the setup request (cache flushed) to USB
controller, any accessing to usb_composite_dev variable will cause the cache line refill, then
when setup transfer is completed, reading the setup data in ctrl_req will gets old value from
cache not from memory.
The ctrl_req is allocated by API dma_alloc_coherent, but u-boot don't have cohernet memory.
so it still needs cache maintain operations before/after HW accessing. Since the cache flush or
invalidate bases on cache line, so when the allocated memory size is not cache line aligned,
potentially it may meet such issue.
This patch modifies the dma_alloc_coherent API to round the size to cache line aligned.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
There is no code for using partition labels in the Allwinner SPL port.
Even so the name is slightly misleading, CONFIG_SPL_LIBDISK_SUPPORT was
meant to guard partition code for the SPL.
Remove the "imply" line in the Kconfig to make this obvious and avoid
unneeded code inclusions, helping to keep the H6 SPL code small.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
