u-boot

88953 commits 9 branches 499 tags 332 MiB

Author	SHA1	Message	Date
Chanho Park	6d78473b3d	timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE timer_get_boot_us function is required to record the boot stages as us-based timestamp. To get a micro-second time from a timer tick, this converts the formula like below to avoid zero result of (tick / rate) part. From: time(us) = (tick / rate) * 1000000 To : time(us) = (tick * 1000) / (rate / 1000) Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>	2023-10-04 17:55:37 +08:00
Bin Meng	9675d92027	riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>	2023-07-12 13:21:40 +08:00

Author

SHA1

Message

Date

Chanho Park

6d78473b3d

timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

timer_get_boot_us function is required to record the boot stages as
us-based timestamp.
To get a micro-second time from a timer tick, this converts the
formula like below to avoid zero result of (tick / rate) part.

From: time(us) = (tick / rate) * 1000000
To  : time(us) = (tick * 1000) / (rate / 1000)

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

2023-10-04 17:55:37 +08:00

Bin Meng

9675d92027

riscv: Rename SiFive CLINT to RISC-V ALINT

As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>

2023-07-12 13:21:40 +08:00

Renamed from drivers/timer/sifive_clint_timer.c (Browse further)

2 commits