Patrick Rudolph <patrick.rudolph@9elements.com> says:
Based on the existing work done by Simon Glass this series adds
support for booting aarch64 devices using ACPI only.
As first target QEMU SBSA support is added, which relies on ACPI
only to boot an OS. As secondary target the Raspberry Pi4 was used,
which is broadly available and allows easy testing of the proposed
solution.
The series is split into ACPI cleanups and code movements, adding
Arm specific ACPI tables and finally SoC and mainboard related
changes to boot a Linux on the QEMU SBSA and RPi4. Currently only the
mandatory ACPI tables are supported, allowing to boot into Linux
without errors.
The QEMU SBSA support is feature complete and provides the same
functionality as the EDK2 implementation.
The changes were tested on real hardware as well on QEMU v9.0:
qemu-system-aarch64 -machine sbsa-ref -nographic -cpu cortex-a57 \
-pflash secure-world.rom \
-pflash unsecure-world.rom
qemu-system-aarch64 -machine raspi4b -kernel u-boot.bin -cpu cortex-a72 \
-smp 4 -m 2G -drive file=raspbian.img,format=raw,index=0 \
-dtb bcm2711-rpi-4-b.dtb -nographic
Tested against FWTS V24.03.00.
Known issues:
- The QEMU rpi4 support is currently limited as it doesn't emulate PCI,
USB or ethernet devices!
- The SMP bringup doesn't work on RPi4, but works in QEMU (Possibly
cache related).
- PCI on RPI4 isn't working on real hardware since the pcie_brcmstb
Linux kernel module doesn't support ACPI yet.
Link: https://lore.kernel.org/r/20241023132116.970117-1-patrick.rudolph@9elements.com
These header files presumably duplicate things already in the U-Boot
devicetree. For now, bring them in to get the ASL code and ACPI table
code to compile.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Matthias Brugger <mbrugger@suse.com>
Cc: Matthias Brugger <mbrugger@suse.com>
Cc: Peter Robinson <pbrobinson@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Add support for the Cadence PCIe Controller present on TI's K3 SoCs.
This driver is an adaptation of the Linux driver.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add support for upstream linux split PCIe node.
Upstream linux have an alternative way to declare PCIe nodes that splits
them in dedicated nodes for each line instead of putting them all in one
node.
Detect this by checking if the mediatek,generic-pciecfg node is passed
as it's used to reference the common address for all the PCIe lines.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Set pcie-phy optional for PCIe gen3. MT7988 doesn't require it and
making it mandatory prevent the driver to correctly probe.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add MediaTek GEN3 PCIe controller support for filogic silicon.
This is adapted from the Linux version of the driver.
Signed-off-by: John Crispin <john@phrozen.org>
[ fix minor problems, fix checkpatch errors ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d, reversing
changes made to 2ee6f3a5f7.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from this driver directory and when needed
add missing include files directly.
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Add support for the IMX8MM SoC by adding driver data with the compatible
string of the GPR controller.
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Since now we have the modern pcie_dw_imx.c driver for iMX SoCs,
encourage people to switch to that for any further new iMX SoC support
or even for the older iMX6 SoCs too.
Suggested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
FDT functions is not working when OF_LIVE is enabled.
Convert fdt parsing functions to ofnode parsing functions
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
This enables 64b BARs if CONFIG_SYS_PCI_64BIT is enabled.
Reviewed-by: Philip Oberfichtner <pro@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Moritz Fischer <moritzf@google.com>
In order to make it easier to move on to dropping common.h from code
directly, remove common.h inclusion from the rest of the header file
which had been including it.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
The host bridge MMIO region is disabled by default due to which MMIO
accesses cause an exception. Fix it by setting the bridge enable bit.
This change is ported from the linux pcie-xilinx driver.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20231116165103.140968-3-mchitale@ventanamicro.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
- Add Board: rk3568 Bananapi R2Pro;
- Update pcie bifurcation support;
- dwc_eth_qos controller support for rk3568 and rk3588;
- Compressed binary support for U-Boot on rockchip platform;
- dts and config updates for different board and soc;
[ trini: Fix conflict on include/spl.h ]
Signed-off-by: Tom Rini <trini@konsulko.com>
Set number of lanes and link width speed control register based on the
num-lanes property.
Code imported almost 1:1 from dw_pcie_setup in mainline linux.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The PCI helpers read only the base address for a PCI region. In some cases
the size is needed as well, e.g. to pass along to a driver which needs to
know the size of its register area.
Update the functions to allow the size to be returned. For serial, record
the information and provided it with the serial_info() call.
A limitation still exists in that the size is not available when OF_LIVE
is enabled, so take account of that in the tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h
Move this out of the common header and include it only where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
When the Broadcom STB PCIe controller is initialized, it must be set
into one of three CLKREQ# modes: "none"/"aspm"/"l1ss". The Linux driver,
through today, hard-codes "aspm" since the vast majority of boards using
this driver have a fixed PCIe bus with the CLKREQ# signal wired up.
The Raspberry Pi CM4, however, can be connected to a plethora of PCIe
devices, some of which do not connect the CLKREQ# line (they just leave
it floating). So "aspm" mode is no longer appropriate in all cases. In
Linux, there is a proposed patchset [1] to determine the proper mode.
This doesn't really make sense in U-Boot's case, so we just change the
assumption from "aspm" to "none" (which is always safe).
This patch DOES resolve a real-world crash that occurs when U-Boot is
running on a Raspberry Pi CM4 installed in slot 3 of a Turing Pi 2
cluster board.
[1]: https://lore.kernel.org/all/20230428223500.23337-1-jim2101024@gmail.com/
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Since the initial U-Boot driver was ported here from Linux, the latter
has had a few changes for robustness/stability. This patch brings over
two of them:
- Do not attempt to access the configuration space of a PCIe device if
the link has gone down, as that will result in an asynchronous SError
interrupt which will crash U-Boot.
- Wait for the recommended 100ms after PERST# is deasserted.
I sent this patch while debugging a crash involving PCIe, but these
are unrelated improvements. I do not believe that this patch fixes any
real-world bug.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Add a new DM driver supporting FTPCI100 IP used in SoC designs.
This implementation is not based on the old non-DM ftpci100 code
dropped from U-Boot.
Enable the driver in sandbox_defconfig to test compilability.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
This function only ever returns 0, but may not assign the second
parameter. Same thing for device_find_next_child(). Do not assign
ret to stop proliferation of this misuse.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Apple hardware supports 64-bit prefetchable memory windows so
enable CONFIG_SYS_PCI_64BIT. This fixes BAR assignments for the
Broadcom Ethernet controller used in some of the desktop machines.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
The PCIe driver for RK3399 is affected by a similar issue that was fixed
for RK35xx in the commit e04b67a7f4 ("pci: pcie_dw_rockchip: release
resources on failing probe").
Resources are not released on failing probe, e.g. regulators may be left
enabled and the ep-gpio may be left in a requested state.
Change to use regulator_set_enable_if_allowed and disable regulators
after failure to keep regulator enable count balanced, ep-gpio is also
released on regulator failure.
Also add support for the vpcie12v-supply, remove unused include and
check return value from dev_read_addr_name.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Get the correct ECAM offset and record the secondary bus
number in Multiple RC case.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
If an error message contains a function name, it should match the name of
the function throwing the message.
Fixes: 7739d93d82 ("pci: Match region flags using a mask")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add pcie driver for StarFive JH7110, Also add PLDA
PCIe controller common driver functions.
Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Acked-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
CONFIG_SPL_PCI_PNP=y without CONFIG_SPL_PCI=y makes no sense.
Fixes: 32f5e9e5c1 ("nvme: pci: Enable for SPL")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The Root Complex BARs default to claim the full 1 GiB memory region on
RK3568, leaving no space for any attached device.
Fix this by disable the unused BAR 0 and BAR 1 of the RC.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[jonas@kwiboo.se: Move to rk_pcie_configure and use PCI_BASE_ADDRESS_0/1 const]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Use a similar pattern and delay values as the linux mainline driver to
speed up failing when nothing is connected.
Reduce fail speed from around 5+ seconds down to around one second on a
Radxa ROCK 3 Model A, where pcie2x1 is probed before pcie3x2 M2 slot.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The vpcie3v3 regulator is typically a fixed regulator controlled using
gpio. Change to use enable and disable calls on the regulator instead
of trying to set a voltage value.
Also remove the delay to match linux driver, for a fixed regulator the
startup-delay-us prop can be used in case a startup delay is needed.
Limited testing on ROCK 3A, ROCK 5B, Quartz64, Odroid-M1 has shown that
this delay was not needed.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Get the config region to use from the reg prop. Also update the
referenced region index used in comment.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In some cases the video ROM may have been enabled previously, such as by
a previous firmware stage. Use the correct address in that case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
A hex value is expected for the VGA mode. Add a 0x prefix, since the #
construct is not supported in SPL. We don't want to add it, due to
code-size constraints.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When video is set up in SPL, U-Boot proper needs to use the correct
parameters so it can write to the display.
Put these in a bloblist so they are available to U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With qemu-x86_64 we need to run the video BIOS while in 32-bit mode, i.e.
SPL. Add a Kconfig option for this, adjust the Makefile rules and use
CONFIG_IS_ENABLED() where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When running the ROM the code is not very helpful when something goes
wrong. Add a little more debugging and some logging of return values to
improve this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Allow PCI autoconfig to be handled in SPL, so that we can set it up
correctly for boards which need to do this before U-Boot proper. This
includes qemu-x64_64 which needs to set up the video device while in
32-bit mode.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Enable NVME and PCI NVMe drivers for SPL builds. Also enable PCI_PNP
for SPL which is required to auto configure the PCIe devices.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
This patch adds the PCIe controller driver for the Xilinx / AMD ZynqMP
NWL PCIe Bridge as root port. The driver source is partly copied from
the Linux PCI driver and modified to enable usage in U-Boot (e.g.
simplified and interrupt support removed).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Pali Rohár <pali@kernel.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Link: https://lore.kernel.org/r/20230525094918.111949-1-sr@denx.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
The PCIe controller on the M2 Pro/Max is different from the one
found on earlier Apple SoCs. Some registers moved and te meaning
of the bits in some other registers changed. But they are still
similar enough to handle both controllers in the same driver.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Add support for max_link_speed specified in the PCI DT binding.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[eugen.hristev@collabora.com: port to latest API, set default correctly,
align to 80 chars]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: switch to dev_read_u32_default]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When U-Boot is the second-stage bootloader, PCI is already set up. We
cannot read the regions from the device tree. There is no point anyway,
since PCI devices have already been allocated according to the regions
and it is not safe for U-Boot to make any changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fixes: f2ebaaa9f3 ("pci: Handle failed calloc in decode_regions()")
Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
