2 commits

Author	SHA1	Message	Date
Venkatesh Yadav Abbarapu	34da258bb0	spi: spi-uclass: Read chipselect and restrict capabilities ... Read chipselect properties from DT which are populated using 'reg' property and save it in plat->cs[] array for later use. Also read multi chipselect capability which is used for parallel-memories and return errors if they are passed on using DT but driver is not capable of handling it. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>	2024-10-09 09:01:54 -06:00
Nick Hawkins	4f689b3d86	spi: gxp_spi: Add GXP SPI controller driver ... The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>	2022-06-22 21:30:05 -04:00