The card-detect GPIO and any other GPIO access currently doesn't work in
U-Boot SPL on any STM32 platform and crashes the SPL. To work around this
problem on AV96 right before release, remove the cd-gpios from DT. This
patch must be reverted right after release, once the proper fix for the
GPIO driver, "gpio: stm32: support gpio ops in SPL", is applied.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
The Jetson Nano Developer Kit is a Tegra X1-based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4GB
of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
used for storage.
HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
Ethernet controller provides onboard network connectivity. NVMe support
has also been added. Env save is at the end of QSPI (4MB-8K).
A 40-pin header on the board can be used to extend the capabilities and
exposed interfaces of the Jetson Nano.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
This adds to the DT the I2C controllers that connect to the board ID EEPROM,
etc. With this change, you can now probe all I2C devices on a TX1 board.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
compatibility with stm32mp15_dhcom_basic_defconfig
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Merge tag 'u-boot-stm32-20200401' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Fix device tree of Avenger96 board from Arrow Electronics and add
compatibility with stm32mp15_dhcom_basic_defconfig
The core and vdd PMIC buck regulators were misconfigured, which caused
instability of the board and malfunction of high-speed interfaces, like
the RGMII. Configure the PMIC correctly to repair these problems. Also,
model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2
and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Add another mux option for DWMAC RGMII, this is used on AV96 board.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
The board has an EEPROM on the same I2C bus as PMIC, at address 0x53.
The EEPROM contains the board MAC address.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: I340a0675c11e4599968b2e3ef0515fb8da8d7b42
Use DT /aliases node to establish a stable phandle to the configuration
EEPROM. This permits the configuration EEPROM to be moved e.g. to a
different address or a different bus. Adjust the board code to handle
new phandle lookup.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it
into the DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: Ia7c454c496f50e3fc4851ec1154f3641c416e98e
The eMMC uses different pinmux for the top four data lines, use such
a pinmux, otherwise it takes a very long time until the test for 8bit
operation times out. And this is the correct pinmux per schematic too.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
The SD uses different pinmux for the D123DIRline, use such a pinmux,
otherwise there is a pinmux collision on the AV96. Add missing SD
voltage regulator switch and enable SDR104 operation.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Add another mux option for SDMMC1 direction pins, in particular
SDMMC1_D123DIR, this is used on AV96 board.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9
("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{};
became pins1{};pins2{};, however the SPL extras were not updated to reflect
that change. Fix this.
This fixes booting from SD1 X9 slot on the AV96 board.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Fixes: 35a54d41d9 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Configure RX and TX bus-width values to use flexspi in octal I/O mode.
If bus-widths are not specified, then single I/O mode is set by default.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Configure RX and TX bus-width values to use flexspi in octal I/O mode.
If bus-widths are not specified, then single I/O mode is set by default.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
lx2160a-qds has 2 micron "mt35xu512aba" flashes of size 64M each
connected on A0 and B1 i.e on CS0 and CS3. Since flashes are connected
on different buses, only one flash can be probed at a time.
Add fspi node properties aligned with LX2160A-RDB fspi properties.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1046A
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Add IIC3 node from mainline Linux DT. This will be further updated in
subsequent DT sync, however adding this node for now is sufficient and
minimal change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Since commit 79030a4861 ("rockchip: Add Single boot image
(with binman, pad_cat)") the following boot regression is seen:
U-Boot 2020.04-rc3-00050-gd16e18ca6c-dirty (Mar 09 2020 - 11:40:07 -0300)
Model: Elgin RV1108 R1 board
DRAM: 128 MiB
initcall sequence 67fd12a0 failed at call 6000b927 (err=-22)
This happens because the above commit missed to include the
"rockchip-u-boot.dtsi" for rv1108, so include this file
like it done for other Rockchip SoC dtsi's.
Fixes: 79030a4861 ("rockchip: Add Single boot image (with binman, pad_cat)")
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In order to make the console pins more robust to noise, activate
the pullups and increase its drive strength.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This parameter "st,phy-cal" becomes optional and when it is
absent the built-in PHY calibration is done.
It is the case in the helper dtsi file "stm32mp15-ddr.dtsi"
except if DDR_PHY_CAL_SKIP is defined.
This patch also impact the ddr interactive mode
- the registers of the param 'phy.cal' are initialized to 0 when
"st,phy-cal" is not present in device tree (default behavior when
DDR_PHY_CAL_SKIP is not activated)
- the info 'cal' field can be use to change the calibration behavior
- cal=1 => use param phy.cal to initialize the PHY, built-in training
is skipped
- cal=0 => param phy.cal is absent, built-in training is used (default)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
This commit manages diversity for STM32M15x SOCs with:
- dedicated files to support all STM32MP15 SOCs family.
The differences between those SOCs are:
-STM32MP151 [1]: common file.
-STM32MP153 [2]: STM32MP151 + CANs + a second CortexA7-CPU.
-STM32MP157 [3]: STM32MP153 + DSI + GPU.
- new files to manage security diversity on STM32MP15x SOCs.
On STM32MP15xY, "Y" gives information:
-Y = A means no cryp IP and no secure boot.
-Y = C means cryp IP + secure boot.
- stm32mp157 pinctrl files to better manage package diversity.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
K3 J721E:
* OSPI boot support
* Support for loading remote cores in R5 SPL
* PMIC ESM Support
* Minor fixes for R5F and C7x remoteproc drivers
K3 AM654:
* Update AVS class 0 voltages.
* Add I2C nodes
DRA7xx/AM57xx:
* Fixed Android boot on AM57xx
AM33/AM43/Davinci:
* switch to driver model for the net and mdio driver for baltos
* Add DM/DTS support for omap video driver
* Enable fastboot on am335x-evm
Instead of resetting the ethernet phy through functions in imx8mq_evk.c, let the
driver reset the phy via dts description adding a reset duration of 10 ms
following atheros 8031's datasheet recommendation.
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
The FEC in the i.MX8MM doesn't support this feature. So don't pretend one
can use it.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Let pinctrl configuration for eMMC node (usdhc1) also be
accessible in SPL.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Before DM_VIDEO conversion this board used 24bpp
display configuration, so use it again.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Update the dummy clock names to use unique identifiers. Otherwise the
previous node just gets overwitten by the next one with the same name.
This fixes eMMC boot not working on J721e-evm.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
With the latest RIOT, there is a different otap delay value for each
speed mode. Add a new binding with every supported speed mode. Also
disable a given speed mode in the host caps if its corresponding
otap-del-sel is not present.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add initial support for the ABB SECU board, which is an ArriaV-based
SoCFPGA system with ethernet and booting from Denali NAND.
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add the "u-boot,dm-pre-reloc" property to the "ti,tilcdc,panel"
compatible node. In this way the video-uclass module can allocate the
amount of memory needed to be assigned to the frame buffer.
For boards that support Linux the property is added to the *-u-boot.dtsi
file since it is a u-boot specific dt flag.
Ran building tests with CONFIG_AM335X_LCD enabled and disabled for the
following configurations:
- brxre1_defconfig --> success
- am335x_guardian_defconfig --> success
- am335x_evm_defconfig --> success
- da850evm_defconfig --> failure with CONFIG_AM335X_LCD enabled
Enabling CONFIG_AM335X_LCD in da850evm_defconfig causes building errors
even without applying the patch. The driver has never been enabled on the
da850 and must be adapted for this platform.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Tested-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Felix Brack <fb@ltec.ch>
The ESM handling on J7 processor board requires routing the
MCU_SAFETY_ERROR signal to the PMIC on the board for critical safety
error handling. The PMIC itself should then reset the board based on
receiving it. Enable the support for the board by adding the esm
node in place.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Main domain ESM support is needed to configure main domain watchdogs
to generate ESM pin events by default. On J7 processor board these
propagate to the PMIC to generate a reset when watchdog expires.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
