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dm: pci: Add a uclass for PCI
Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
parent
aab6724c90
commit
ff3e077bd2
10 changed files with 1081 additions and 14 deletions
289
include/pci.h
289
include/pci.h
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@ -457,12 +457,15 @@ static inline void pci_set_region(struct pci_region *reg,
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typedef int pci_dev_t;
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#define PCI_BUS(d) (((d) >> 16) & 0xff)
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#define PCI_DEV(d) (((d) >> 11) & 0x1f)
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#define PCI_FUNC(d) (((d) >> 8) & 0x7)
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#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
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#define PCI_ANY_ID (~0)
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#define PCI_BUS(d) (((d) >> 16) & 0xff)
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#define PCI_DEV(d) (((d) >> 11) & 0x1f)
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#define PCI_FUNC(d) (((d) >> 8) & 0x7)
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#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
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#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
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#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
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#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
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#define PCI_VENDEV(v, d) (((v) << 16) | (d))
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#define PCI_ANY_ID (~0)
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struct pci_device_id {
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unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
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@ -495,7 +498,12 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev
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* Structure of a PCI controller (host bridge)
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*/
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struct pci_controller {
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#ifdef CONFIG_DM_PCI
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struct udevice *bus;
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struct udevice *ctlr;
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#else
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struct pci_controller *next;
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#endif
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int first_busno;
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int last_busno;
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@ -511,7 +519,7 @@ struct pci_controller {
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struct pci_config_table *config_table;
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void (*fixup_irq)(struct pci_controller *, pci_dev_t);
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#ifndef CONFIG_DM_PCI
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/* Low-level architecture-dependent routines */
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int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
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int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
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@ -519,17 +527,21 @@ struct pci_controller {
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int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
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int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
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int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
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#endif
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/* Used by auto config */
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struct pci_region *pci_mem, *pci_io, *pci_prefetch;
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/* Used by ppc405 autoconfig*/
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struct pci_region *pci_fb;
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#ifndef CONFIG_DM_PCI
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int current_busno;
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void *priv_data;
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#endif
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};
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#ifndef CONFIG_DM_PCI
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static inline void pci_set_ops(struct pci_controller *hose,
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int (*read_byte)(struct pci_controller*,
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pci_dev_t, int where, u8 *),
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@ -550,6 +562,7 @@ static inline void pci_set_ops(struct pci_controller *hose,
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hose->write_word = write_word;
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hose->write_dword = write_dword;
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}
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#endif
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#ifdef CONFIG_PCI_INDIRECT_BRIDGE
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extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
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@ -602,12 +615,14 @@ extern int pci_hose_write_config_word(struct pci_controller *hose,
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extern int pci_hose_write_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int where, u32 val);
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#ifndef CONFIG_DM_PCI
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extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
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extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
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extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
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extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
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extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
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extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
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#endif
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extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
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pci_dev_t dev, int where, u8 *val);
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@ -719,5 +734,265 @@ int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev);
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pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
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struct pci_device_id *ids, int *indexp);
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/* Access sizes for PCI reads and writes */
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enum pci_size_t {
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PCI_SIZE_8,
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PCI_SIZE_16,
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PCI_SIZE_32,
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};
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struct udevice;
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#ifdef CONFIG_DM_PCI
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/**
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* struct pci_child_platdata - information stored about each PCI device
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*
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* Every device on a PCI bus has this per-child data.
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*
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* It can be accessed using dev_get_parentdata(dev) if dev->parent is a
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* PCI bus (i.e. UCLASS_PCI)
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*
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* @devfn: Encoded device and function index - see PCI_DEVFN()
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* @vendor: PCI vendor ID (see pci_ids.h)
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* @device: PCI device ID (see pci_ids.h)
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* @class: PCI class, 3 bytes: (base, sub, prog-if)
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*/
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struct pci_child_platdata {
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int devfn;
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unsigned short vendor;
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unsigned short device;
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unsigned int class;
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};
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/* PCI bus operations */
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struct dm_pci_ops {
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/**
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* read_config() - Read a PCI configuration value
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*
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* PCI buses must support reading and writing configuration values
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* so that the bus can be scanned and its devices configured.
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*
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* Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.
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* If bridges exist it is possible to use the top-level bus to
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* access a sub-bus. In that case @bus will be the top-level bus
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* and PCI_BUS(bdf) will be a different (higher) value
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*
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* @bus: Bus to read from
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* @bdf: Bus, device and function to read
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* @offset: Byte offset within the device's configuration space
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* @valuep: Place to put the returned value
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* @size: Access size
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* @return 0 if OK, -ve on error
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*/
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int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
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ulong *valuep, enum pci_size_t size);
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/**
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* write_config() - Write a PCI configuration value
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*
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* @bus: Bus to write to
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* @bdf: Bus, device and function to write
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* @offset: Byte offset within the device's configuration space
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* @value: Value to write
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* @size: Access size
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* @return 0 if OK, -ve on error
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*/
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int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
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ulong value, enum pci_size_t size);
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};
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/* Get access to a PCI bus' operations */
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#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
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/**
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* pci_bind_bus_devices() - scan a PCI bus and bind devices
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*
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* Scan a PCI bus looking for devices. Bind each one that is found. If
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* devices are already bound that match the scanned devices, just update the
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* child data so that the device can be used correctly (this happens when
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* the device tree describes devices we expect to see on the bus).
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*
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* Devices that are bound in this way will use a generic PCI driver which
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* does nothing. The device can still be accessed but will not provide any
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* driver interface.
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*
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* @bus: Bus containing devices to bind
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* @return 0 if OK, -ve on error
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*/
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int pci_bind_bus_devices(struct udevice *bus);
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/**
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* pci_auto_config_devices() - configure bus devices ready for use
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*
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* This works through all devices on a bus by scanning the driver model
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* data structures (normally these have been set up by pci_bind_bus_devices()
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* earlier).
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*
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* Space is allocated for each PCI base address register (BAR) so that the
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* devices are mapped into memory and I/O space ready for use.
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*
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* @bus: Bus containing devices to bind
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* @return 0 if OK, -ve on error
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*/
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int pci_auto_config_devices(struct udevice *bus);
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/**
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* pci_bus_find_bdf() - Find a device given its PCI bus address
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*
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* @bdf: PCI device address: bus, device and function -see PCI_BDF()
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* @devp: Returns the device for this address, if found
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* @return 0 if OK, -ENODEV if not found
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*/
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int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
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/**
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* pci_bus_find_devfn() - Find a device on a bus
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*
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* @find_devfn: PCI device address (device and function only)
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* @devp: Returns the device for this address, if found
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* @return 0 if OK, -ENODEV if not found
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*/
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int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
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struct udevice **devp);
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/**
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* pci_get_ff() - Returns a mask for the given access size
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*
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* @size: Access size
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* @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
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* PCI_SIZE_32
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*/
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int pci_get_ff(enum pci_size_t size);
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/**
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* pci_bus_find_devices () - Find devices on a bus
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*
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* @bus: Bus to search
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* @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
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* @indexp: Pointer to device index to find. To find the first matching
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* device, pass 0; to find the second, pass 1, etc. This
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* parameter is decremented for each non-matching device so
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* can be called repeatedly.
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* @devp: Returns matching device if found
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* @return 0 if found, -ENODEV if not
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*/
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int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
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int *indexp, struct udevice **devp);
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/**
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* pci_find_device_id() - Find a device on any bus
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*
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* @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
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* @index: Index number of device to find, 0 for the first match, 1 for
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* the second, etc.
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* @devp: Returns matching device if found
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* @return 0 if found, -ENODEV if not
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*/
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int pci_find_device_id(struct pci_device_id *ids, int index,
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struct udevice **devp);
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/**
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* dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
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*
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* This probes the given bus which causes it to be scanned for devices. The
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* devices will be bound but not probed.
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*
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* @hose specifies the PCI hose that will be used for the scan. This is
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* always a top-level bus with uclass UCLASS_PCI. The bus to scan is
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* in @bdf, and is a subordinate bus reachable from @hose.
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*
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* @hose: PCI hose to scan
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* @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
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* @return 0 if OK, -ve on error
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*/
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int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf);
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/**
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* pci_bus_read_config() - Read a configuration value from a device
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*
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* TODO(sjg@chromium.org): We should be able to pass just a device and have
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* it do the right thing. It would be good to have that function also.
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*
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* @bus: Bus to read from
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* @bdf: PCI device address: bus, device and function -see PCI_BDF()
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* @valuep: Place to put the returned value
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* @size: Access size
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* @return 0 if OK, -ve on error
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*/
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int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
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unsigned long *valuep, enum pci_size_t size);
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/**
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* pci_bus_write_config() - Write a configuration value to a device
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*
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* @bus: Bus to write from
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* @bdf: PCI device address: bus, device and function -see PCI_BDF()
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* @value: Value to write
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* @size: Access size
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* @return 0 if OK, -ve on error
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*/
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int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
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unsigned long value, enum pci_size_t size);
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/*
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* The following functions provide access to the above without needing the
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* size parameter. We are trying to encourage the use of the 8/16/32-style
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* functions, rather than byte/word/dword. But both are supported.
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*/
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int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
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/* Compatibility with old naming */
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static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
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u32 value)
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{
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return pci_write_config32(pcidev, offset, value);
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}
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int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
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/* Compatibility with old naming */
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static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
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u16 value)
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{
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return pci_write_config16(pcidev, offset, value);
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}
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int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
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/* Compatibility with old naming */
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static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
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u8 value)
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{
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return pci_write_config8(pcidev, offset, value);
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}
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int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
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/* Compatibility with old naming */
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static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
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u32 *valuep)
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{
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return pci_read_config32(pcidev, offset, valuep);
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}
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int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
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/* Compatibility with old naming */
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static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
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u16 *valuep)
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{
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return pci_read_config16(pcidev, offset, valuep);
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}
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int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
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/* Compatibility with old naming */
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static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
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u8 *valuep)
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{
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return pci_read_config8(pcidev, offset, valuep);
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _PCI_H */
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