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Merge patch series "Add OPP_LOW support for J7200"
Aniket Limaye <a-limaye@ti.com> says: This series adds OPP_LOW spec data in k3_avs driver and enables a config option to select the OPP_LOW performance point. J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance Points as per (7.5 Operating Performance Points) section in the Datasheet [0]. - A72SS/MSMC at 2 GHz/1GHz operation must use OPP_NOM. - A72SS/MSMC at 1 GHz/500 MHz operation can use OPP_NOM or OPP_LOW voltage (though OPP_LOW voltage is recommended to reduce power consumption). The actual OPP voltage for the device is read from the efuse and updated in k3_avs_probe(). The default j7200 devicetree and k3_avs driver set OPP_NOM spec frequency and voltage. In the board init file, if K3_OPP_LOW config is enabled, Check if OPP_LOW AVS voltage read from efuse is valid and update frequency (A72 and MSMC) and voltage (VDD_CPU) as per the OPP_LOW spec. [0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet) Test logs: https://gist.github.com/aniket-l/328ad93ed60c2419ed7be9f85e6b6075 - With series applied on master and CONFIG_K3_OPP_LOW enabled in j7200_evm_r5_defconfig - Logs shown with and without efuse register programmed for OPP_0 (Errors out if OPP_0 not found, programs OPP_LOW spec if found) - Voltage update verified using 'i2c md 0x4c 0xe' in u-boot - Frequency update verified using 'k3conf clock dump' in linux Link: https://lore.kernel.org/r/20241119003617.1871183-1-a-limaye@ti.com
This commit is contained in:
Tom Rini
commit
fe76d868f7
6 changed files with 143 additions and 6 deletions
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@ -23,11 +23,12 @@
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<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
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<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
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resets = <&k3_reset 202 0>;
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clocks = <&k3_clks 61 1>, <&k3_clks 202 2>;
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clock-names = "gtc", "core";
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assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>;
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assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>;
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assigned-clock-rates = <2000000000>, <200000000>;
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clocks = <&k3_clks 61 1>, <&k3_clks 202 2>, <&k3_clks 4 1> ;
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clock-names = "gtc", "core", "msmc";
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assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 4 1>,
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<&k3_clks 323 0>;
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assigned-clock-parents= <0>, <0>, <0>, <&k3_clks 323 2>;
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assigned-clock-rates = <2000000000>, <200000000>, <1000000000>;
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ti,sci = <&dmsc>;
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ti,sci-proc-id = <32>;
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ti,sci-host-id = <10>;
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@ -19,6 +19,7 @@
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#include <fdtdec.h>
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#include <mmc.h>
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#include <remoteproc.h>
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#include <k3-avs.h>
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#include "../sysfw-loader.h"
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#include "../common.h"
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@ -39,6 +40,12 @@
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#define NB_THREADMAP_BIT0 BIT(0)
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#define NB_THREADMAP_BIT1 BIT(1)
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/* TISCI DEV ID for A72, MSMC Clock */
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#define DEV_A72SS0_CORE0_0_ID 202
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#define DEV_A72SS0_CORE0_0_ARM_CLK_CLK_ID 2
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#define DEV_A72SS0_CORE0_ID 4
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#define DEV_A72SS0_CORE0_MSMC_CLK_ID 1
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#ifdef CONFIG_K3_LOAD_SYSFW
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struct fwl_data cbass_hc_cfg0_fwls[] = {
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#if defined(CONFIG_TARGET_J721E_R5_EVM)
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@ -147,6 +154,78 @@ static void setup_navss_nb(void)
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writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
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}
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#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
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static int get_clock_index_by_dev_id(ofnode node, u32 dev_id, u32 clk_id)
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{
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ofnode clknode;
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int count, i;
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struct ofnode_phandle_args phandle_args;
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clknode = ofnode_by_compatible(ofnode_null(), "ti,k2g-sci-clk");
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if (!ofnode_valid(clknode)) {
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printf("%s: clock-controller not found\n", __func__);
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return -ENODEV;
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}
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count = ofnode_count_phandle_with_args(node, "assigned-clocks", "#clock-cells", 0);
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for (i = 0; i < count; i++) {
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if (ofnode_parse_phandle_with_args(node, "assigned-clocks",
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"#clock-cells", 0, i, &phandle_args)) {
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printf("%s: Could not parse assigned-clocks at index %d\n", __func__, i);
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continue;
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}
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if (ofnode_equal(clknode, phandle_args.node) &&
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phandle_args.args[0] == dev_id && phandle_args.args[1] == clk_id)
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return i;
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}
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return -1;
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}
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static int fdt_fixup_a72ss_clock_frequency(void)
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{
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int index, size;
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u32 *rates;
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ofnode node;
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node = ofnode_by_compatible(ofnode_null(), "ti,am654-rproc");
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if (!ofnode_valid(node)) {
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printf("%s: A72 not found\n", __func__);
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return -ENODEV;
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}
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rates = fdt_getprop_w(ofnode_to_fdt(node), ofnode_to_offset(node),
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"assigned-clock-rates", &size);
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if (!rates) {
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printf("%s: Wrong A72 assigned-clocks-rates configuration\n", __func__);
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return -1;
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}
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/* Update A72 Clock Frequency to OPP_LOW spec */
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index = get_clock_index_by_dev_id(node,
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DEV_A72SS0_CORE0_0_ID,
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DEV_A72SS0_CORE0_0_ARM_CLK_CLK_ID);
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if (index < 0 || index >= (size / sizeof(u32))) {
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printf("%s: Wrong A72 assigned-clocks configuration\n", __func__);
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return -1;
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}
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rates[index] = cpu_to_fdt32(1000000000);
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printf("Changed A72 CPU frequency to %dHz in DT\n", 1000000000);
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/* Update MSMC Clock Frequency to OPP_LOW spec */
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index = get_clock_index_by_dev_id(node,
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DEV_A72SS0_CORE0_ID,
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DEV_A72SS0_CORE0_MSMC_CLK_ID);
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if (index < 0 || index >= (size / sizeof(u32))) {
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printf("%s: Wrong A72 assigned-clocks configuration\n", __func__);
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return -1;
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}
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rates[index] = cpu_to_fdt32(500000000);
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printf("Changed MSMC frequency to %dHz in DT\n", 500000000);
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return 0;
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}
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#endif
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/*
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* This uninitialized global variable would normal end up in the .bss section,
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* but the .bss is cleared between writing and reading this variable, so move
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@ -301,8 +380,19 @@ void board_init_f(ulong dummy)
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#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
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ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
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&dev);
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if (ret)
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if (ret) {
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printf("AVS init failed: %d\n", ret);
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} else if (IS_ENABLED(CONFIG_K3_OPP_LOW)) {
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ret = k3_avs_check_opp(dev, J721E_VDD_MPU, AM6_OPP_LOW);
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if (ret) {
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printf("OPP_LOW: k3_avs_check_opp failed: %d\n", ret);
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} else {
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ret = fdt_fixup_a72ss_clock_frequency();
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if (ret)
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printf("OPP_LOW: fdt_fixup_a72ss_clock_frequency failed: %d\n",
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ret);
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}
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}
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#endif
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#if defined(CONFIG_K3_J721E_DDRSS)
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@ -1,6 +1,13 @@
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config K3_LOAD_SYSFW
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bool
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config K3_OPP_LOW
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depends on ARCH_K3 && K3_AVS0
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bool "Enable OPP_LOW on supported TI K3 SoCs"
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help
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Enabling this will allow Socs with the proper efuse to run at a lower
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MPU core voltage and adjust frequency according to SoC TRM
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config K3_QOS
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bool "Enable Quality of Service (QoS) Settings for TI K3 SoCs"
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default y if SOC_K3_AM62A7
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@ -102,6 +102,7 @@ CONFIG_K3_SEC_PROXY=y
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CONFIG_FS_LOADER=y
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CONFIG_SPL_FS_LOADER=y
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CONFIG_K3_AVS0=y
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# CONFIG_K3_OPP_LOW is not set
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CONFIG_SUPPORT_EMMC_BOOT=y
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CONFIG_SPL_MMC_HS400_SUPPORT=y
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CONFIG_MMC_SDHCI=y
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@ -121,6 +121,11 @@ static int k3_avs_program_voltage(struct k3_avs_privdata *priv,
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if (!vd->supply)
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return -ENODEV;
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if (!volt) {
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dev_err(priv->dev, "No efuse found for opp_%d\n", opp_id);
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return -EINVAL;
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}
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vd->opp = opp_id;
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vd->flags |= VD_FLAG_INIT_DONE;
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@ -192,6 +197,33 @@ static int match_opp(struct vd_data *vd, u32 freq)
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return -EINVAL;
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}
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/**
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* k3_check_opp: Check for presence of opp efuse
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* @dev: AVS device
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* @vdd_id: voltage domain ID
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* @opp_id: opp id to check if voltage is present
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*
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* Checks to see if an opp has voltage. k3_avs probe will populate
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* voltage data if efuse is present. Returns 0 if data is valid.
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*/
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int k3_avs_check_opp(struct udevice *dev, int vdd_id, int opp_id)
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{
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struct k3_avs_privdata *priv = dev_get_priv(dev);
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struct vd_data *vd;
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int volt;
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vd = get_vd(priv, vdd_id);
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if (!vd)
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return -EINVAL;
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volt = vd->opps[opp_id].volt;
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if (volt)
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return 0;
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printf("No efuse found for opp_%d\n", opp_id);
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return -EINVAL;
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}
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/**
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* k3_avs_notify_freq: Notify clock rate change towards AVS subsystem
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* @dev_id: Device ID for the clock to be changed
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@ -501,6 +533,10 @@ static struct vd_data j721e_vd_data[] = {
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.dev_id = 202, /* J721E_DEV_A72SS0_CORE0 */
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.clk_id = 2, /* ARM clock */
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.opps = {
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[AM6_OPP_LOW] = {
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.volt = 0, /* voltage TBD after OPP fuse reading */
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.freq = 1000000000,
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},
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[AM6_OPP_NOM] = {
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.volt = 880000, /* TBD in DM */
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.freq = 2000000000,
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@ -20,11 +20,13 @@
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#define NUM_OPPS 4
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#define AM6_OPP_LOW 0
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#define AM6_OPP_NOM 1
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#define AM6_OPP_OD 2
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#define AM6_OPP_TURBO 3
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int k3_avs_set_opp(struct udevice *dev, int vdd_id, int opp_id);
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int k3_avs_notify_freq(int dev_id, int clk_id, u32 freq);
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int k3_avs_check_opp(struct udevice *dev, int vdd_id, int opp_id);
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#endif
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