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imx8mm-cl-iot-gate: Add support for the Realtek RTL8211E PHY
Newer imx8mm-cl-iot-gate versions are populated with a Realtek RTL8211E PHY instead of the Atheros AR8033. Adapted Compulab's patch from: https://github.com/compulab-yokneam/meta-bsp-imx8mm/blob/iot-gate-imx8_5.10.72/recipes-bsp/u-boot/compulab/imx8mm/0125-imx8mm-net-enable-phy-Realtek-RTL8211E.patch to support both PHYs in U-Boot. Signed-off-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Fabio Estevam
Fabio Estevam
parent
93bfb458f4
commit
fb95661116
2 changed files with 104 additions and 4 deletions
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@ -8,6 +8,7 @@
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#include <efi_loader.h>
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#include <env.h>
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#include <extension_board.h>
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#include <fdt_support.h>
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#include <hang.h>
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#include <i2c.h>
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#include <init.h>
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@ -30,6 +31,8 @@
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DECLARE_GLOBAL_DATA_PTR;
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static int fec_phyaddr = -1;
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#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
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struct efi_fw_image fw_images[] = {
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#if defined(CONFIG_TARGET_IMX8MM_CL_IOT_GATE)
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@ -109,10 +112,72 @@ static int setup_fec(void)
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return 0;
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}
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#define FDT_PHYADDR "/soc@0/bus@30800000/ethernet@30be0000/mdio/ethernet-phy@0"
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#define FLIP_32B(val) (((val >> 24) & 0xff) | ((val << 8) & 0xff0000) | ((val >> 8) & 0xff00) | ((val << 24) & 0xff000000))
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static int fdt_set_fec_phy_addr(void *blob)
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{
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u32 val;
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if (fec_phyaddr < 0)
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return -EINVAL;
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val = FLIP_32B(fec_phyaddr);
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return fdt_find_and_setprop(blob, FDT_PHYADDR, "reg", (const void *)&val,
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sizeof(val), 0);
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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fdt_set_fec_phy_addr(blob);
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return 0;
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}
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/*
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* These are specific ID, purposed to distiguish between PHY vendors.
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* These values are not equal to real vendors' OUI (half of MAC address)
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*/
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#define OUI_PHY_ATHEROS 0x1374
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#define OUI_PHY_REALTEK 0x0732
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int board_phy_config(struct phy_device *phydev)
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{
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if (IS_ENABLED(CONFIG_FEC_MXC)) {
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unsigned int model, rev, oui;
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int phyid1, phyid2;
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unsigned int reg;
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if (!IS_ENABLED(CONFIG_FEC_MXC))
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return 0;
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phyid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1);
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if (phyid1 < 0) {
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printf("%s: PHYID1 registry read fail %i\n", __func__, phyid1);
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return phyid1;
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}
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phyid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2);
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if (phyid2 < 0) {
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printf("%s: PHYID2 registry read fail %i\n", __func__, phyid2);
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return phyid2;
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}
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reg = phyid2 | phyid1 << 16;
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if (reg == 0xffff) {
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printf("%s: There is no device @%i\n", __func__, phydev->addr);
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return -ENODEV;
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}
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rev = reg & 0xf;
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reg >>= 4;
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model = reg & 0x3f;
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reg >>= 6;
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oui = reg;
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debug("%s: PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
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__func__, phydev->addr, oui, model, rev);
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switch (oui) {
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case OUI_PHY_ATHEROS:
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/* enable rgmii rxc skew and phy mode select to RGMII copper */
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printf("phy: AR803x@%x\t", phydev->addr);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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@ -120,10 +185,45 @@ int board_phy_config(struct phy_device *phydev)
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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break;
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case OUI_PHY_REALTEK:
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printf("phy: RTL8211E@%x\t", phydev->addr);
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/* RTL8211E-VB-CG - add TX and RX delay */
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unsigned short val;
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x07);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0xa4);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1c);
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val |= (0x1 << 13) | (0x1 << 12) | (0x1 << 11);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, val);
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/* LEDs: set to extension page */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0007);
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/* extension Page44 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x002c);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, 0x0430);//LCR
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1a, 0x0010);//LACR
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/*
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* To disable EEE LED mode (blinking .4s/2s)
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* Extension Page5
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*/
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0005);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x05, 0x8b82);//magic const
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phy_write(phydev, MDIO_DEVAD_NONE, 0x06, 0x052b);//magic const
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x00);// Back to Page0
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break;
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default:
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printf("%s: ERROR: unknown PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
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__func__, phydev->addr, oui, model, rev);
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return -ENOSYS;
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}
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fec_phyaddr = phydev->addr;
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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@ -136,7 +136,7 @@
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#define CFG_SYS_FSL_USDHC_NUM 2
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#define CFG_SYS_FSL_ESDHC_ADDR 0
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#define CFG_FEC_MXC_PHYADDR 0
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#define CFG_FEC_MXC_PHYADDR -1 /* Auto search of PHY on MII */
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/* USB Configs */
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#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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