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https://github.com/u-boot/u-boot.git
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i2c: mxc: move to new subsystem
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
This commit is contained in:
trem
Heiko Schocher
parent
815a76f2ef
commit
fac9640895
6 changed files with 93 additions and 63 deletions
11
README
11
README
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@ -2003,6 +2003,17 @@ CBFS (Coreboot Filesystem) support
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- CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
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- CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
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- drivers/i2c/i2c_mxc.c
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- activate this driver with CONFIG_SYS_I2C_MXC
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- define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
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- define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
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- define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
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- define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
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- define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
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- define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
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If thoses defines are not set, default value is 100000
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for speed, and 0 for slave.
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additional defines:
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CONFIG_SYS_NUM_I2C_BUSES
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@ -94,7 +94,7 @@ void enable_usboh3_clk(bool enable)
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MXC_CCM_CCGR2_USBOH3_60M(cg));
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}
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#ifdef CONFIG_I2C_MXC
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#ifdef CONFIG_SYS_I2C_MXC
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/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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{
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@ -48,7 +48,7 @@ void enable_usboh3_clk(unsigned char enable)
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}
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#ifdef CONFIG_I2C_MXC
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#ifdef CONFIG_SYS_I2C_MXC
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/* i2c_num can be from 0 - 2 */
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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{
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@ -16,7 +16,7 @@ COBJS-y = iomux-v3.o
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endif
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ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
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COBJS-y += timer.o cpu.o speed.o
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COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
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COBJS-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
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endif
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ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
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COBJS-y += misc.o
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@ -14,7 +14,6 @@ COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
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COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
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COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
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COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
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COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
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COBJS-$(CONFIG_I2C_MXS) += mxs_i2c.o
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COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
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COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
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@ -28,6 +27,7 @@ COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
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COBJS-$(CONFIG_SYS_I2C) += i2c_core.o
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COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
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COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
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COBJS-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
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COBJS-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
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COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
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COBJS-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
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@ -102,6 +102,28 @@ static u16 i2c_clk_div[50][2] = {
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};
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#endif
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#ifndef CONFIG_SYS_MXC_I2C1_SPEED
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#define CONFIG_SYS_MXC_I2C1_SPEED 100000
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#endif
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#ifndef CONFIG_SYS_MXC_I2C2_SPEED
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#define CONFIG_SYS_MXC_I2C2_SPEED 100000
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#endif
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#ifndef CONFIG_SYS_MXC_I2C3_SPEED
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#define CONFIG_SYS_MXC_I2C3_SPEED 100000
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#endif
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#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
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#define CONFIG_SYS_MXC_I2C1_SLAVE 0
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#endif
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#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
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#define CONFIG_SYS_MXC_I2C2_SLAVE 0
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#endif
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#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
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#define CONFIG_SYS_MXC_I2C3_SLAVE 0
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#endif
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/*
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* Calculate and set proper clock divider
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*/
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@ -153,21 +175,6 @@ static int bus_i2c_set_bus_speed(void *base, int speed)
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return 0;
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}
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/*
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* Get I2C Speed
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*/
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static unsigned int bus_i2c_get_bus_speed(void *base)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
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u8 clk_idx = readb(&i2c_regs->ifdr);
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u8 clk_div;
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for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
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;
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return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0];
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}
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#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
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#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
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#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
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@ -410,20 +417,30 @@ struct sram_data {
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*/
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static struct sram_data __attribute__((section(".data"))) srdata;
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void *get_base(void)
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{
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#ifdef CONFIG_SYS_I2C_BASE
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#ifdef CONFIG_I2C_MULTI_BUS
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void *ret = srdata.i2c_data[srdata.curr_i2c_bus].base;
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if (ret)
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return ret;
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#endif
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return (void *)CONFIG_SYS_I2C_BASE;
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#elif defined(CONFIG_I2C_MULTI_BUS)
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return srdata.i2c_data[srdata.curr_i2c_bus].base;
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static void * const i2c_bases[] = {
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#if defined(CONFIG_MX25)
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(void *)IMX_I2C_BASE,
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(void *)IMX_I2C2_BASE,
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(void *)IMX_I2C3_BASE
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#elif defined(CONFIG_MX27)
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(void *)IMX_I2C1_BASE,
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(void *)IMX_I2C2_BASE
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#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
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defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
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defined(CONFIG_MX6)
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(void *)I2C1_BASE_ADDR,
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(void *)I2C2_BASE_ADDR,
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(void *)I2C3_BASE_ADDR
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#elif defined(CONFIG_VF610)
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(void *)I2C0_BASE_ADDR
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#else
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return srdata.i2c_data[0].base;
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#error "architecture not supported"
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#endif
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};
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void *i2c_get_base(struct i2c_adapter *adap)
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{
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return i2c_bases[adap->hwadapnr];
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}
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static struct i2c_parms *i2c_get_parms(void *base)
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@ -448,39 +465,26 @@ static int i2c_idle_bus(void *base)
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return 0;
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}
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#ifdef CONFIG_I2C_MULTI_BUS
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unsigned int i2c_get_bus_num(void)
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static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
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uint addr, int alen, uint8_t *buffer,
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int len)
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{
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return srdata.curr_i2c_bus;
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return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
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}
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int i2c_set_bus_num(unsigned bus_idx)
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static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
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uint addr, int alen, uint8_t *buffer,
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int len)
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{
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if (bus_idx >= ARRAY_SIZE(srdata.i2c_data))
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return -1;
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if (!srdata.i2c_data[bus_idx].base)
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return -1;
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srdata.curr_i2c_bus = bus_idx;
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return 0;
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}
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#endif
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int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
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{
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return bus_i2c_read(get_base(), chip, addr, alen, buf, len);
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}
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int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
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{
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return bus_i2c_write(get_base(), chip, addr, alen, buf, len);
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return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
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}
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/*
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* Test if a chip at a given address responds (probe the chip)
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*/
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int i2c_probe(uchar chip)
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static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
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{
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return bus_i2c_write(get_base(), chip, 0, 0, NULL, 0);
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return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
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}
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void bus_i2c_init(void *base, int speed, int unused,
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@ -510,23 +514,38 @@ void bus_i2c_init(void *base, int speed, int unused,
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/*
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* Init I2C Bus
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*/
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void i2c_init(int speed, int unused)
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static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
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{
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bus_i2c_init(get_base(), speed, unused, NULL, NULL);
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bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
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}
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/*
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* Set I2C Speed
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*/
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int i2c_set_bus_speed(unsigned int speed)
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static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
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{
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return bus_i2c_set_bus_speed(get_base(), speed);
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return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
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}
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/*
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* Get I2C Speed
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* Register mxc i2c adapters
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*/
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unsigned int i2c_get_bus_speed(void)
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{
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return bus_i2c_get_bus_speed(get_base());
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}
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U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
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mxc_i2c_read, mxc_i2c_write,
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mxc_i2c_set_bus_speed,
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CONFIG_SYS_MXC_I2C1_SPEED,
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CONFIG_SYS_MXC_I2C1_SLAVE, 0)
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U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
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mxc_i2c_read, mxc_i2c_write,
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mxc_i2c_set_bus_speed,
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CONFIG_SYS_MXC_I2C2_SPEED,
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CONFIG_SYS_MXC_I2C2_SLAVE, 1)
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#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
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defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
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defined(CONFIG_MX6)
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U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
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mxc_i2c_read, mxc_i2c_write,
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mxc_i2c_set_bus_speed,
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CONFIG_SYS_MXC_I2C3_SPEED,
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CONFIG_SYS_MXC_I2C3_SLAVE, 2)
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#endif
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