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cosmetic: spell fixes etc.

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Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
Acked-by: Detlev Zundel <dzu@denx.de>
This commit is contained in:
Michael Jones 2011-07-14 22:09:28 +00:00 • committed by Wolfgang Denk
parent 857d9ea67a
commit f9a78b8d4f
6 changed files with 13 additions and 13 deletions
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6
README
View file

@ -1723,12 +1723,12 @@ The following options need to be configured:
=> =>
If you now switch to the new I2C Bus 3 with "i2c dev 3" If you now switch to the new I2C Bus 3 with "i2c dev 3"
u-boot sends First the Commando to the mux@70 to enable u-boot first sends the command to the mux@70 to enable
channel 6, and then the Commando to the mux@71 to enable channel 6, and then the command to the mux@71 to enable
the channel 4. the channel 4.
After that, you can use the "normal" i2c commands as After that, you can use the "normal" i2c commands as
usual, to communicate with your I2C devices behind usual to communicate with your I2C devices behind
the 2 muxes. the 2 muxes.
This option is actually implemented for the bitbanging This option is actually implemented for the bitbanging

2
arch/arm/include/asm/global_data.h
View file

@ -24,7 +24,7 @@
#ifndef __ASM_GBL_DATA_H #ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H
/* /*
* The following data structure is placed in some memory wich is * The following data structure is placed in some memory which is
* available very early after boot (like DPRAM on MPC8xx/MPC82xx, or * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
* some locked parts of the data cache) to allow for a minimum set of * some locked parts of the data cache) to allow for a minimum set of
* global variables during system initialization (until we have set * global variables during system initialization (until we have set

2
common/cmd_eeprom.c
View file

@ -250,7 +250,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn
/* /*
* For a FRAM device there is no limit on the number of the * For a FRAM device there is no limit on the number of the
* bytes that can be ccessed with the single read or write * bytes that can be accessed with the single read or write
* operation. * operation.
*/ */
#if !defined(CONFIG_SYS_I2C_FRAM) #if !defined(CONFIG_SYS_I2C_FRAM)

4
common/cmd_i2c.c
View file

@ -1397,8 +1397,8 @@ static int i2c_mux_get_busid (void)
return tmp; return tmp;
} }
/* Analyses a Muxstring and sends immediately the /* Analyses a Muxstring and immediately sends the
Commands to the Muxes. Runs from Flash. commands to the muxes. Runs from flash.
*/ */
int i2c_mux_ident_muxstring_f (uchar *buf) int i2c_mux_ident_muxstring_f (uchar *buf)
{ {

2
drivers/i2c/omap24xx_i2c.c
View file

@ -399,7 +399,7 @@ static void wait_for_bb (void)
int timeout = I2C_TIMEOUT; int timeout = I2C_TIMEOUT;
u16 stat; u16 stat;
writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/ writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) { while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
writew (stat, &i2c_base->stat); writew (stat, &i2c_base->stat);
udelay(1000); udelay(1000);