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driver/ddr/fsl: Fix DDR4 driver

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When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.

Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2014-09-11 13:32:06 -07:00
parent 8aeb893a8e
commit f80d6472b4
2 changed files with 8 additions and 4 deletions
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3
drivers/ddr/fsl/fsl_ddr_gen4.c
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@ -216,7 +216,7 @@ step2:
* For example, 2GB on 666MT/s 64-bit bus takes about 402ms
* Let's wait for 800ms
*/
bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
(get_ddr_freq(0) >> 20)) << 2;
@ -233,5 +233,4 @@ step2:
if (timeout <= 0)
printf("Waiting for D_INIT timeout. Memory may not work.\n");
}