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configs: Resync with savedefconfig

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Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2020-07-28 08:46:52 -04:00
parent 1db942b67d
commit f7d0ae9c63
1005 changed files with 1050 additions and 1310 deletions
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69
scripts/config_whitelist.txt
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@ -78,7 +78,6 @@ CONFIG_AT91_GPIO_PULLUP
CONFIG_AT91_LED
CONFIG_AT91_WANTS_COMMON_PHY
CONFIG_ATAPI
CONFIG_ATI
CONFIG_ATI_RADEON_FB
CONFIG_ATM
CONFIG_ATMEL_LCD
@ -189,7 +188,6 @@ CONFIG_CLK_1000_400_200
CONFIG_CLK_800_330_165
CONFIG_CLK_DEBUG
CONFIG_CLOCKS
CONFIG_CLOCKS_IN_MHZ
CONFIG_CLOCK_SYNTHESIZER
CONFIG_CM922T_XA10
CONFIG_CMDLINE_PS_SUPPORT
@ -201,7 +199,6 @@ CONFIG_CM_SPD_DETECT
CONFIG_CM_T335
CONFIG_CM_T3X
CONFIG_CM_T43
CONFIG_CM_T54
CONFIG_CM_TCRAM
CONFIG_CNTL
CONFIG_COLDFIRE
@ -242,7 +239,6 @@ CONFIG_CPU_PXA25X
CONFIG_CPU_PXA26X
CONFIG_CPU_PXA27X
CONFIG_CPU_PXA300
CONFIG_CPU_R8000
CONFIG_CPU_SH7722
CONFIG_CPU_SH7751
CONFIG_CPU_SH7752
@ -298,7 +294,6 @@ CONFIG_DEEP_SLEEP
CONFIG_DEFAULT
CONFIG_DEFAULT_CONSOLE
CONFIG_DEFAULT_IMMR
CONFIG_DEF_HWCONFIG
CONFIG_DESIGNWARE_ETH
CONFIG_DEVELOP
CONFIG_DEVICE_TREE_LIST
@ -327,7 +322,6 @@ CONFIG_DNET_AUTONEG_TIMEOUT
CONFIG_DP_DDR_CTRL
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
CONFIG_DP_DDR_NUM_CTRLS
CONFIG_DRAM_2G
CONFIG_DRAM_TIMINGS_
CONFIG_DRIVER_AT91EMAC
CONFIG_DRIVER_AT91EMAC_PHYADDR
@ -401,12 +395,10 @@ CONFIG_EHCI_IS_TDI
CONFIG_EHCI_MMIO_BIG_ENDIAN
CONFIG_EHCI_MXS_PORT0
CONFIG_EHCI_MXS_PORT1
CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
CONFIG_EMU
CONFIG_ENABLE_36BIT_PHYS
CONFIG_ENABLE_MMU
CONFIG_ENABLE_MUST_CHECK
CONFIG_ENABLE_WARN_DEPRECATED
CONFIG_ENV_ADDR_FLEX
CONFIG_ENV_CALLBACK_LIST_DEFAULT
CONFIG_ENV_CALLBACK_LIST_STATIC
@ -569,7 +561,6 @@ CONFIG_FSL_PMIC_CS
CONFIG_FSL_PMIC_MODE
CONFIG_FSL_QIXIS
CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
CONFIG_FSL_QIXIS_V2
CONFIG_FSL_SATA_V2
CONFIG_FSL_SDHC_V2_3
CONFIG_FSL_SDRAM_TYPE
@ -642,7 +633,6 @@ CONFIG_HAS_ETH0
CONFIG_HAS_ETH1
CONFIG_HAS_ETH2
CONFIG_HAS_ETH3
CONFIG_HAS_ETH4
CONFIG_HAS_ETH5
CONFIG_HAS_ETH7
CONFIG_HAS_FEC
@ -811,7 +801,6 @@ CONFIG_I2C
CONFIG_I2C_CHIPADDRESS
CONFIG_I2C_CMD_TREE
CONFIG_I2C_ENV_EEPROM_BUS
CONFIG_I2C_FPGA
CONFIG_I2C_GSC
CONFIG_I2C_MAC_OFFSET
CONFIG_I2C_MBB_TIMEOUT
@ -833,7 +822,6 @@ CONFIG_ICS307_REFCLK_HZ
CONFIG_IDE_PREINIT
CONFIG_IDE_RESET
CONFIG_IDE_SWAP_IO
CONFIG_IDT8T49N222A
CONFIG_ID_EEPROM
CONFIG_IMA
CONFIG_IMX
@ -926,7 +914,6 @@ CONFIG_KM_UPDATE_UBOOT
CONFIG_KONA
CONFIG_KONA_GPIO
CONFIG_KONA_RESET_S
CONFIG_KPROBES
CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE
CONFIG_KSNAV_NETCP_PDMA_RX_BASE
CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM
@ -1268,7 +1255,6 @@ CONFIG_PCI_SKIP_HOST_BRIDGE
CONFIG_PCI_SYS_BUS
CONFIG_PCI_SYS_PHYS
CONFIG_PCI_SYS_SIZE
CONFIG_PCNET
CONFIG_PEN_ADDR_BIG_ENDIAN
CONFIG_PERIF1_FREQ
CONFIG_PERIF2_FREQ
@ -1283,16 +1269,7 @@ CONFIG_PHY_INTERFACE_MODE
CONFIG_PHY_IRAM_BASE
CONFIG_PHY_M88E1111
CONFIG_PHY_MODE_NEED_CHANGE
CONFIG_PHY_RESET
CONFIG_PHY_RESET_DELAY
CONFIG_PIXIS_BRDCFG0_SPI
CONFIG_PIXIS_BRDCFG0_USB2
CONFIG_PIXIS_BRDCFG1_AUDCLK_11
CONFIG_PIXIS_BRDCFG1_AUDCLK_12
CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK
CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK
CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI
CONFIG_PIXIS_BRDCFG1_TDM
CONFIG_PIXIS_SGMII_CMD
CONFIG_PL011_CLOCK
CONFIG_PL011_SERIAL_RLCR
@ -1372,7 +1349,6 @@ CONFIG_QUOTA
CONFIG_R7780MP
CONFIG_RAMBOOT
CONFIG_RAMBOOTCOMMAND
CONFIG_RAMBOOTCOMMAND_TFTP
CONFIG_RAMBOOT_NAND
CONFIG_RAMBOOT_PBL
CONFIG_RAMBOOT_SDCARD
@ -1574,7 +1550,6 @@ CONFIG_SOC_OMAP3430
CONFIG_SOFT_I2C_GPIO_SCL
CONFIG_SOFT_I2C_GPIO_SDA
CONFIG_SOFT_I2C_READ_REPEATED_START
CONFIG_SPARSE_RCU_POINTER
CONFIG_SPD_EEPROM
CONFIG_SPEAR300
CONFIG_SPEAR310
@ -1688,8 +1663,6 @@ CONFIG_SRIO_PCIE_BOOT_SLAVE
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
CONFIG_SSD_BR_PRELIM
CONFIG_SSD_OR_PRELIM
CONFIG_SSE2
CONFIG_SSI1_FREQ
CONFIG_SSI2_FREQ
@ -1838,9 +1811,6 @@ CONFIG_SYS_CH7301_I2C
CONFIG_SYS_CKEN
CONFIG_SYS_CLK
CONFIG_SYS_CLKTL_CBCDR
CONFIG_SYS_CLK_100
CONFIG_SYS_CLK_100_DDR_100
CONFIG_SYS_CLK_100_DDR_133
CONFIG_SYS_CLK_DIV
CONFIG_SYS_CLK_FREQ_C100
CONFIG_SYS_CLK_FREQ_C110
@ -2017,7 +1987,6 @@ CONFIG_SYS_DCSR_COP_CCP_ADDR
CONFIG_SYS_DCSR_DCFG_ADDR
CONFIG_SYS_DCSR_DCFG_OFFSET
CONFIG_SYS_DCU_ADDR
CONFIG_SYS_DDR1_CS0_BNDS
CONFIG_SYS_DDR2_CFG_1A
CONFIG_SYS_DDR2_CFG_1B
CONFIG_SYS_DDR2_CFG_2
@ -2057,7 +2026,6 @@ CONFIG_SYS_DDR_CLK_CONTROL
CONFIG_SYS_DDR_CLK_CTRL
CONFIG_SYS_DDR_CLK_CTRL_1000
CONFIG_SYS_DDR_CLK_CTRL_1200
CONFIG_SYS_DDR_CLK_CTRL_1333
CONFIG_SYS_DDR_CLK_CTRL_667
CONFIG_SYS_DDR_CLK_CTRL_800
CONFIG_SYS_DDR_CLK_CTRL_900
@ -2066,17 +2034,11 @@ CONFIG_SYS_DDR_CONFIG_2
CONFIG_SYS_DDR_CONFIG_256
CONFIG_SYS_DDR_CONTROL
CONFIG_SYS_DDR_CONTROL2
CONFIG_SYS_DDR_CONTROL_1333
CONFIG_SYS_DDR_CONTROL_2
CONFIG_SYS_DDR_CONTROL_2_1333
CONFIG_SYS_DDR_CONTROL_2_800
CONFIG_SYS_DDR_CONTROL_800
CONFIG_SYS_DDR_CPO
CONFIG_SYS_DDR_CS0_BNDS
CONFIG_SYS_DDR_CS0_CONFIG
CONFIG_SYS_DDR_CS0_CONFIG_1333
CONFIG_SYS_DDR_CS0_CONFIG_2
CONFIG_SYS_DDR_CS0_CONFIG_800
CONFIG_SYS_DDR_CS1_BNDS
CONFIG_SYS_DDR_CS1_CONFIG
CONFIG_SYS_DDR_CS1_CONFIG_2
@ -2092,7 +2054,6 @@ CONFIG_SYS_DDR_INIT_EXT_ADDR
CONFIG_SYS_DDR_INTERVAL
CONFIG_SYS_DDR_INTERVAL_1000
CONFIG_SYS_DDR_INTERVAL_1200
CONFIG_SYS_DDR_INTERVAL_1333
CONFIG_SYS_DDR_INTERVAL_667
CONFIG_SYS_DDR_INTERVAL_800
CONFIG_SYS_DDR_INTERVAL_900
@ -2101,14 +2062,12 @@ CONFIG_SYS_DDR_MODE2
CONFIG_SYS_DDR_MODE_1
CONFIG_SYS_DDR_MODE_1_1000
CONFIG_SYS_DDR_MODE_1_1200
CONFIG_SYS_DDR_MODE_1_1333
CONFIG_SYS_DDR_MODE_1_667
CONFIG_SYS_DDR_MODE_1_800
CONFIG_SYS_DDR_MODE_1_900
CONFIG_SYS_DDR_MODE_2
CONFIG_SYS_DDR_MODE_2_1000
CONFIG_SYS_DDR_MODE_2_1200
CONFIG_SYS_DDR_MODE_2_1333
CONFIG_SYS_DDR_MODE_2_667
CONFIG_SYS_DDR_MODE_2_800
CONFIG_SYS_DDR_MODE_2_900
@ -2135,41 +2094,32 @@ CONFIG_SYS_DDR_SR_CNTR
CONFIG_SYS_DDR_TIMING_0
CONFIG_SYS_DDR_TIMING_0_1000
CONFIG_SYS_DDR_TIMING_0_1200
CONFIG_SYS_DDR_TIMING_0_1333
CONFIG_SYS_DDR_TIMING_0_667
CONFIG_SYS_DDR_TIMING_0_800
CONFIG_SYS_DDR_TIMING_0_900
CONFIG_SYS_DDR_TIMING_1
CONFIG_SYS_DDR_TIMING_1_1000
CONFIG_SYS_DDR_TIMING_1_1200
CONFIG_SYS_DDR_TIMING_1_1333
CONFIG_SYS_DDR_TIMING_1_667
CONFIG_SYS_DDR_TIMING_1_800
CONFIG_SYS_DDR_TIMING_1_900
CONFIG_SYS_DDR_TIMING_2
CONFIG_SYS_DDR_TIMING_2_1000
CONFIG_SYS_DDR_TIMING_2_1200
CONFIG_SYS_DDR_TIMING_2_1333
CONFIG_SYS_DDR_TIMING_2_667
CONFIG_SYS_DDR_TIMING_2_800
CONFIG_SYS_DDR_TIMING_2_900
CONFIG_SYS_DDR_TIMING_3
CONFIG_SYS_DDR_TIMING_3_1000
CONFIG_SYS_DDR_TIMING_3_1200
CONFIG_SYS_DDR_TIMING_3_1333
CONFIG_SYS_DDR_TIMING_3_667
CONFIG_SYS_DDR_TIMING_3_800
CONFIG_SYS_DDR_TIMING_3_900
CONFIG_SYS_DDR_TIMING_4
CONFIG_SYS_DDR_TIMING_4_1333
CONFIG_SYS_DDR_TIMING_4_800
CONFIG_SYS_DDR_TIMING_5
CONFIG_SYS_DDR_TIMING_5_1333
CONFIG_SYS_DDR_TIMING_5_800
CONFIG_SYS_DDR_WRITE_DATA_DELAY
CONFIG_SYS_DDR_WRLVL_CNTL
CONFIG_SYS_DDR_WRLVL_CONTROL
CONFIG_SYS_DDR_WRLVL_CONTROL_1333
CONFIG_SYS_DDR_WRLVL_CONTROL_667
CONFIG_SYS_DDR_WRLVL_CONTROL_800
CONFIG_SYS_DDR_ZQ_CNTL
@ -2225,7 +2175,6 @@ CONFIG_SYS_ELBC_BASE_PHYS
CONFIG_SYS_ELO3_DMA3
CONFIG_SYS_EMAC_TI_CLKDIV
CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
CONFIG_SYS_ENABLE_PADS_ALL
CONFIG_SYS_ENET_BD_BASE
CONFIG_SYS_ENV_ADDR
CONFIG_SYS_ENV_SECT_SIZE
@ -2296,7 +2245,6 @@ CONFIG_SYS_FLASH_VERIFY_AFTER_WRITE
CONFIG_SYS_FLASH_WRITE_TOUT
CONFIG_SYS_FLYCNFG_VAL
CONFIG_SYS_FM1_10GEC1_PHY_ADDR
CONFIG_SYS_FM1_10GEC2_PHY_ADDR
CONFIG_SYS_FM1_CLK
CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR
CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
@ -2309,8 +2257,6 @@ CONFIG_SYS_FM1_DTSEC4_PHY_ADDR
CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR
CONFIG_SYS_FM1_DTSEC_MDIO_ADDR
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR
CONFIG_SYS_FM1_QSGMII11_PHY_ADDR
CONFIG_SYS_FM1_QSGMII21_PHY_ADDR
CONFIG_SYS_FM1_TGEC_MDIO_ADDR
@ -2346,7 +2292,6 @@ CONFIG_SYS_FPGAREG_RESET
CONFIG_SYS_FPGAREG_RESET_CODE
CONFIG_SYS_FPGA_AMASK
CONFIG_SYS_FPGA_BASE
CONFIG_SYS_FPGA_BASE_PHYS
CONFIG_SYS_FPGA_CHECK_BUSY
CONFIG_SYS_FPGA_CHECK_CTRLC
CONFIG_SYS_FPGA_CHECK_ERROR
@ -2442,9 +2387,7 @@ CONFIG_SYS_FSL_DRAM_SIZE1
CONFIG_SYS_FSL_DRAM_SIZE2
CONFIG_SYS_FSL_DRAM_SIZE3
CONFIG_SYS_FSL_DSPI_BE
CONFIG_SYS_FSL_DSP_CCSRBAR
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS
CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR
CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET
CONFIG_SYS_FSL_DSP_DDR_ADDR
@ -2785,7 +2728,6 @@ CONFIG_SYS_I2C_PCA953X_ADDR2
CONFIG_SYS_I2C_PCA953X_ADDR3
CONFIG_SYS_I2C_PCA953X_WIDTH
CONFIG_SYS_I2C_PCA9553_ADDR
CONFIG_SYS_I2C_PCA9555_ADDR
CONFIG_SYS_I2C_PCA9557_ADDR
CONFIG_SYS_I2C_PCF8574A_ADDR
CONFIG_SYS_I2C_PEX8518_ADDR
@ -2995,7 +2937,6 @@ CONFIG_SYS_MALLOC_BASE
CONFIG_SYS_MALLOC_SIMPLE
CONFIG_SYS_MAMR
CONFIG_SYS_MAPLE
CONFIG_SYS_MAPLE_MEM_PHYS
CONFIG_SYS_MAPPED_RAM_BASE
CONFIG_SYS_MASTER_CLOCK
CONFIG_SYS_MATRIX_EBI0CSA_VAL
@ -3546,9 +3487,6 @@ CONFIG_SYS_PIXIS_VBOOT_MASK
CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
CONFIG_SYS_PJPAR
CONFIG_SYS_PL310_BASE
CONFIG_SYS_PLATFORM_SRAM_BASE
CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS
CONFIG_SYS_PLATFORM_SRAM_SIZE
CONFIG_SYS_PLLAR_VAL
CONFIG_SYS_PLLBR_VAL
CONFIG_SYS_PLLCR
@ -3805,8 +3743,6 @@ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR
CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS
CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR
CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS
CONFIG_SYS_SSD_BASE
CONFIG_SYS_SSD_BASE_PHYS
CONFIG_SYS_SST_SECT
CONFIG_SYS_SST_SECTSZ
CONFIG_SYS_STACK_SIZE
@ -3993,7 +3929,6 @@ CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
CONFIG_TESTPIN_MASK
CONFIG_TESTPIN_REG
CONFIG_TEST_LIST_SORT
CONFIG_TFP410_I2C_ADDR
CONFIG_TFTP_FILE_NAME_MAX_LEN
CONFIG_TFTP_PORT
CONFIG_TFTP_TSIZE
@ -4023,8 +3958,6 @@ CONFIG_TSEC_TBI
CONFIG_TSEC_TBICR_SETTINGS
CONFIG_TWL6030_INPUT
CONFIG_TWL6030_POWER
CONFIG_TWR
CONFIG_TWR_P1025
CONFIG_TX_DESCR_NUM
CONFIG_TZSW_RESERVED_DRAM_SIZE
CONFIG_UART_BR_PRELIM
@ -4180,7 +4113,6 @@ CONFIG_VSC7385_ENET
CONFIG_VSC7385_IMAGE
CONFIG_VSC7385_IMAGE_SIZE
CONFIG_VSC9953
CONFIG_VSC_CROSSBAR
CONFIG_WATCHDOG_NOWAYOUT
CONFIG_WATCHDOG_PRESC
CONFIG_WATCHDOG_RC
@ -4206,5 +4138,4 @@ CONFIG_YAFFS_UTIL
CONFIG_YAFFS_WINCE
CONFIG_YELLOW_LED
CONFIG_ZLT
CONFIG_ZM7300
CONFIG_eTSEC_MDIO_BUS