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Fix MMC access on Sabrelite
It appears that MMC access on the Sabrelite has been broken since
cdcaee9518:
Loading Environment from MMC... Card did not respond to voltage select!
*** Warning - No block device, using default environment
Remove the board_mmc_init() and related entries now that we should be
using DM_MMC, add PINCTRL so that things work as expected.
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Troy Kisky <troy.kisky@boundarydevices.com>
This commit is contained in:
Martyn Welch
Stefano Babic
parent
0e15165bc4
commit
f7ac30b042
2 changed files with 3 additions and 72 deletions
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@ -25,7 +25,6 @@
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#include <asm/mach-imx/spi.h>
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#include <asm/mach-imx/spi.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/video.h>
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#include <asm/mach-imx/video.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <fsl_esdhc_imx.h>
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#include <micrel.h>
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#include <micrel.h>
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#include <miiphy.h>
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#include <miiphy.h>
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@ -161,26 +160,6 @@ static iomux_v3_cfg_t const usdhc2_pads[] = {
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IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
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};
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, NO_PAD_CTRL), /* CD */
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};
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
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IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, NO_PAD_CTRL), /* CD */
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};
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static iomux_v3_cfg_t const enet_pads1[] = {
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static iomux_v3_cfg_t const enet_pads1[] = {
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IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
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IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
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IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
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IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
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@ -305,57 +284,6 @@ int board_ehci_power(int port, int on)
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#endif
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#endif
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#ifdef CONFIG_FSL_ESDHC_IMX
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static struct fsl_esdhc_cfg usdhc_cfg[2] = {
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{USDHC3_BASE_ADDR},
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{USDHC4_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
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IMX_GPIO_NR(2, 6);
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gpio_direction_input(gp_cd);
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return !gpio_get_value(gp_cd);
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}
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int board_mmc_init(bd_t *bis)
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{
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int ret;
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u32 index = 0;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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usdhc_cfg[0].max_bus_width = 4;
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usdhc_cfg[1].max_bus_width = 4;
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for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
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switch (index) {
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case 0:
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SETUP_IOMUX_PADS(usdhc3_pads);
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break;
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case 1:
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SETUP_IOMUX_PADS(usdhc4_pads);
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break;
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default:
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printf("Warning: you configured more USDHC controllers"
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"(%d) then supported by the board (%d)\n",
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index + 1, CONFIG_SYS_FSL_USDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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#ifdef CONFIG_MXC_SPI
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#ifdef CONFIG_MXC_SPI
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int board_spi_cs_gpio(unsigned bus, unsigned cs)
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int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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{
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@ -28,6 +28,7 @@ CONFIG_CMD_GPT=y
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# CONFIG_RANDOM_UUID is not set
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# CONFIG_RANDOM_UUID is not set
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CONFIG_CMD_I2C=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_MMC=y
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# CONFIG_CMD_PINMUX is not set
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CONFIG_CMD_SATA=y
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CONFIG_CMD_SATA=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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@ -55,6 +56,8 @@ CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_MII=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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CONFIG_SPI=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_MXC_SPI=y
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CONFIG_MXC_SPI=y
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