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mvebe: Migrate CONFIG_DDR_LOG_LEVEL to Kconfig

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Move this specific option to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-08-21 13:50:15 -04:00
parent 94752f5fb1
commit f66a3fde38
2 changed files with 14 additions and 4 deletions
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14
arch/arm/mach-mvebu/Kconfig
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@ -197,6 +197,20 @@ config DDR_32BIT
endchoice endchoice
config DDR_LOG_LEVEL
int "DDR training code log level"
depends on ARMADA_XP
default 0
range 0 3
help
Amount of information provided on error while running the DDR
training code. At level 0, provides an error code in a case of
failure, RL, WL errors and other algorithm failure. At level 1,
provides the D-Unit setup (SPD/Static configuration). At level 2,
provides the windows margin as a results of DQS centeralization.
At level 3, rovides the windows margin of each DQ as a results of
DQS centeralization.
config SYS_BOARD config SYS_BOARD
default "clearfog" if TARGET_CLEARFOG default "clearfog" if TARGET_CLEARFOG
default "helios4" if TARGET_HELIOS4 default "helios4" if TARGET_HELIOS4

4
drivers/ddr/marvell/axp/ddr3_axp_config.h
View file

@ -16,11 +16,7 @@
* Level 3: Provides the windows margin of each DQ as a results of DQS * Level 3: Provides the windows margin of each DQ as a results of DQS
* centeralization * centeralization
*/ */
#ifdef CONFIG_DDR_LOG_LEVEL
#define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL #define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL
#else
#define DDR3_LOG_LEVEL 0
#endif
#define DDR3_PBS 1 #define DDR3_PBS 1