Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-04-24 14:25:56 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

clk: renesas: Allow reconfiguring SDHI clock on Gen3

Browse source 
The SDHI clock must be configured differently for HS200/HS400/SDR104
modes. Add support for reconfiguring the SDHI clock settings into the
clock driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut 2018-10-30 17:54:20 +01:00 • committed by Marek Vasut
parent 952061352a
commit f58d6771a2
1 changed files with 3 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
drivers/clk/renesas/clk-rcar-gen3.c
View file

@ -107,7 +107,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
return renesas_clk_get_parent(clk, info, parent); return renesas_clk_get_parent(clk, info, parent);
} }
static int gen3_clk_setup_sdif_div(struct clk *clk) static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
{ {
struct gen3_clk_priv *priv = dev_get_priv(clk->dev); struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
struct cpg_mssr_info *info = priv->info; struct cpg_mssr_info *info = priv->info;
@ -133,7 +133,7 @@ static int gen3_clk_setup_sdif_div(struct clk *clk)
debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset); debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
writel(1, priv->base + core->offset); writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset);
return 0; return 0;
} }
@ -141,10 +141,6 @@ static int gen3_clk_setup_sdif_div(struct clk *clk)
static int gen3_clk_enable(struct clk *clk) static int gen3_clk_enable(struct clk *clk)
{ {
struct gen3_clk_priv *priv = dev_get_priv(clk->dev); struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
int ret = gen3_clk_setup_sdif_div(clk);
if (ret)
return ret;
return renesas_clk_endisable(clk, priv->base, true); return renesas_clk_endisable(clk, priv->base, true);
} }
@ -328,7 +324,7 @@ static ulong gen3_clk_get_rate(struct clk *clk)
static ulong gen3_clk_set_rate(struct clk *clk, ulong rate) static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
{ {
/* Force correct SD-IF divider configuration if applicable */ /* Force correct SD-IF divider configuration if applicable */
gen3_clk_setup_sdif_div(clk); gen3_clk_setup_sdif_div(clk, rate);
return gen3_clk_get_rate64(clk); return gen3_clk_get_rate64(clk);
} }