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board: developerbox: fix mem_map setup timing

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The setup of global variable mem_map was moved into enable_caches()
by commit a70c75caba ("board: developerbox: move mem_map setup later")
since U-Boot was directly booted from NOR flash in XIP
and bss is not yet available in dram_init() at that time.
This has a problem, mem_map variable is used by
the get_page_table_size() to calculate the page table size,
but get_page_table_size() is called earlier than enable_caches()
which fills mem_map variable. With that, U-Boot fails to boot when
64GB DIMM is installed.

Currently U-Boot on the Developerbox board is not booted in XIP
and bss is available in dram_init(), let's move mem_map setup
in dram_init().

Signed-off-by: Masahisa Kojima <kojima.masahisa@socionext.com>
This commit is contained in:
Masahisa Kojima 2024-03-06 15:11:10 +09:00 • committed by Tom Rini
parent 5b05266928
commit f56d9a385c
1 changed files with 21 additions and 39 deletions
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60
board/socionext/developerbox/developerbox.c
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@ -125,10 +125,29 @@ int dram_init(void)
struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
struct draminfo_entry *ent = synquacer_draminfo->entry; struct draminfo_entry *ent = synquacer_draminfo->entry;
unsigned long size = 0; unsigned long size = 0;
int i; struct mm_region *mr;
int i, ri;
for (i = 0; i < synquacer_draminfo->nr_regions; i++) if (synquacer_draminfo->nr_regions < 1) {
log_err("Failed to get correct DRAM information\n");
return -EINVAL;
}
for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
if (i >= MAX_DDR_REGIONS)
break;
ri = DDR_REGION_INDEX(i);
mem_map[ri].phys = ent[i].base;
mem_map[ri].size = ent[i].size;
mem_map[ri].virt = mem_map[ri].phys;
size += ent[i].size; size += ent[i].size;
if (i == 0)
continue;
mr = &mem_map[DDR_REGION_INDEX(0)];
mem_map[ri].attrs = mr->attrs;
}
gd->ram_size = size; gd->ram_size = size;
gd->ram_base = ent[0].base; gd->ram_base = ent[0].base;
@ -162,43 +181,6 @@ int dram_init_banksize(void)
return 0; return 0;
} }
void build_mem_map(void)
{
struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
struct draminfo_entry *ent = synquacer_draminfo->entry;
struct mm_region *mr;
int i, ri;
if (synquacer_draminfo->nr_regions < 1) {
log_err("Failed to get correct DRAM information\n");
return;
}
/* Update memory region maps */
for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
if (i >= MAX_DDR_REGIONS)
break;
ri = DDR_REGION_INDEX(i);
mem_map[ri].phys = ent[i].base;
mem_map[ri].size = ent[i].size;
mem_map[ri].virt = mem_map[ri].phys;
if (i == 0)
continue;
mr = &mem_map[DDR_REGION_INDEX(0)];
mem_map[ri].attrs = mr->attrs;
}
}
void enable_caches(void)
{
build_mem_map();
icache_enable();
dcache_enable();
}
int print_cpuinfo(void) int print_cpuinfo(void)
{ {
printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n"); printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n");