Merge patch series "Select CONFIG_64BIT for sandbox64 and x86_64"

Andrew Goodbody <andrew.goodbody@linaro.org> says:

Picking up a series from Dan Carpenter and applying requested
changes for v2.

I had previously set CONFIG_64BIT for arm64.  This patchset does the
same thing for sandbox and x86_64.  (Mips and riscv were already
doing it).  This CONFIG option is used in the Makefile to determine
if it's a 32 or 64 bit system for the CHECKER.

Makefile
  1052  # the checker needs the correct machine size
  1053  CHECKFLAGS += $(if $(CONFIG_64BIT),-m64,-m32)

Link: https://lore.kernel.org/r/20241216180736.1933807-1-andrew.goodbody@linaro.org

arch/Kconfig

@@ -37,6 +37,14 @@ config 32BIT
 
 config 64BIT
 	bool
+	help
+	  Indicates that U-Boot proper will be built for a 64 bit
+	  architecture.
+
+config SPL_64BIT
+	bool
+	help
+	  Indicates that SPL will be built for a 64 bit architecture.
 
 config SYS_CACHELINE_SIZE
 	int

arch/arm/Kconfig

@@ -7,6 +7,7 @@ config SYS_ARCH
 config ARM64
 	bool
 	select 64BIT
+	select SPL_64BIT if SPL
 	select PHYS_64BIT
 	select SYS_CACHE_SHIFT_6
 	imply SPL_SEPARATE_BSS

arch/mips/Kconfig

@@ -211,6 +211,7 @@ config CPU_MIPS64_R1
 	bool "MIPS64 Release 1"
 	depends on SUPPORTS_CPU_MIPS64_R1
 	select 64BIT
+	select SPL_64BIT if SPL
 	help
 	  Choose this option to build a kernel for release 1 through 5 of the
 	  MIPS64 architecture.
@@ -219,6 +220,7 @@ config CPU_MIPS64_R2
 	bool "MIPS64 Release 2"
 	depends on SUPPORTS_CPU_MIPS64_R2
 	select 64BIT
+	select SPL_64BIT if SPL
 	help
 	  Choose this option to build a kernel for release 2 through 5 of the
 	  MIPS64 architecture.
@@ -227,6 +229,7 @@ config CPU_MIPS64_R6
 	bool "MIPS64 Release 6"
 	depends on SUPPORTS_CPU_MIPS64_R6
 	select 64BIT
+	select SPL_64BIT if SPL
 	help
 	  Choose this option to build a kernel for release 6 or later of the
 	  MIPS64 architecture.
@@ -235,6 +238,7 @@ config CPU_MIPS64_OCTEON
 	bool "Marvell Octeon series of CPUs"
 	depends on SUPPORTS_CPU_MIPS64_OCTEON
 	select 64BIT
+	select SPL_64BIT if SPL
 	help
 	 Choose this option for Marvell Octeon CPUs.  These CPUs are between
 	 MIPS64 R5 and R6 with other extensions.

arch/riscv/Kconfig

@@ -129,6 +129,7 @@ config ARCH_RV32I
 config ARCH_RV64I
 	bool "RV64I"
 	select 64BIT
+	select SPL_64BIT if SPL
 	select PHYS_64BIT
 	help
 	  Choose this option to target the RV64I base integer instruction set.

arch/sandbox/Kconfig

@@ -46,6 +46,8 @@ config HOST_32BIT
 
 config HOST_64BIT
 	def_bool $(cc-define,_LP64)
+	select 64BIT
+	select SPL_64BIT if SPL
 
 config HOST_HAS_SDL
 	def_bool $(success,sdl2-config --version)

arch/sandbox/include/asm/io.h

@@ -39,13 +39,13 @@ void sandbox_write(void *addr, unsigned int val, enum sandboxio_size_t size);
 #define readb(addr) sandbox_read((const void *)addr, SB_SIZE_8)
 #define readw(addr) sandbox_read((const void *)addr, SB_SIZE_16)
 #define readl(addr) sandbox_read((const void *)addr, SB_SIZE_32)
-#ifdef CONFIG_SANDBOX64
+#ifdef CONFIG_64BIT
 #define readq(addr) sandbox_read((const void *)addr, SB_SIZE_64)
 #endif
 #define writeb(v, addr) sandbox_write((void *)addr, v, SB_SIZE_8)
 #define writew(v, addr) sandbox_write((void *)addr, v, SB_SIZE_16)
 #define writel(v, addr) sandbox_write((void *)addr, v, SB_SIZE_32)
-#ifdef CONFIG_SANDBOX64
+#ifdef CONFIG_64BIT
 #define writeq(v, addr) sandbox_write((void *)addr, v, SB_SIZE_64)
 #endif
 

arch/x86/Kconfig

@@ -44,6 +44,7 @@ endchoice
 
 config X86_64
 	bool
+	select 64BIT
 
 config SPL_X86_64
 	bool

common/bloblist.c

@@ -576,14 +576,17 @@ int bloblist_maybe_init(void)
 
 int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig)
 {
-	ulong version = BLOBLIST_REGCONV_VER;
+	u64 version = BLOBLIST_REGCONV_VER;
 	ulong sigval;
 
-	sigval = (IS_ENABLED(CONFIG_64BIT)) ?
+	if ((IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_SPL_BUILD)) ||
-			((BLOBLIST_MAGIC & ((1UL << BLOBLIST_REGCONV_SHIFT_64) - 1)) |
+			(IS_ENABLED(CONFIG_SPL_64BIT) && IS_ENABLED(CONFIG_SPL_BUILD))) {
-			 ((version  & BLOBLIST_REGCONV_MASK) << BLOBLIST_REGCONV_SHIFT_64)) :
+		sigval = ((BLOBLIST_MAGIC & ((1ULL << BLOBLIST_REGCONV_SHIFT_64) - 1)) |
-			((BLOBLIST_MAGIC & ((1UL << BLOBLIST_REGCONV_SHIFT_32) - 1)) |
+			 ((version  & BLOBLIST_REGCONV_MASK) << BLOBLIST_REGCONV_SHIFT_64));
+	} else {
+		sigval = ((BLOBLIST_MAGIC & ((1UL << BLOBLIST_REGCONV_SHIFT_32) - 1)) |
 			 ((version  & BLOBLIST_REGCONV_MASK) << BLOBLIST_REGCONV_SHIFT_32));
+	}
 
 	if (rzero || rsig != sigval ||
 	    rfdt != (ulong)bloblist_find(BLOBLISTT_CONTROL_FDT, 0)) {

include/limits.h

@@ -9,7 +9,8 @@
 #define UINT32_MAX  0xffffffffU
 #define UINT64_MAX  0xffffffffffffffffULL
 
-#ifdef CONFIG_64BIT
+#if (defined(CONFIG_64BIT) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_64BIT) && defined(CONFIG_SPL_BUILD))
     #define UINTPTR_MAX UINT64_MAX
 #else
     #define UINTPTR_MAX UINT32_MAX

test/lib/str.c

@@ -224,13 +224,13 @@ static int str_itoa(struct unit_test_state *uts)
 	ut_asserteq_str("4294967295", simple_itoa(0xffffffff));
 
 	/* Use #ifdef here to avoid a compiler warning on 32-bit machines */
-#ifdef CONFIG_PHYS_64BIT
+#ifdef CONFIG_64BIT
 	if (sizeof(ulong) == 8) {
 		ut_asserteq_str("9223372036854775807",
 				simple_itoa((1UL << 63) - 1));
 		ut_asserteq_str("18446744073709551615", simple_itoa(-1));
 	}
-#endif /* CONFIG_PHYS_64BIT */
+#endif /* CONFIG_64BIT */
 
 	return 0;
 }
@@ -244,13 +244,13 @@ static int str_xtoa(struct unit_test_state *uts)
 	ut_asserteq_str("ffffffff", simple_xtoa(0xffffffff));
 
 	/* Use #ifdef here to avoid a compiler warning on 32-bit machines */
-#ifdef CONFIG_PHYS_64BIT
+#ifdef CONFIG_64BIT
 	if (sizeof(ulong) == 8) {
 		ut_asserteq_str("7fffffffffffffff",
 				simple_xtoa((1UL << 63) - 1));
 		ut_asserteq_str("ffffffffffffffff", simple_xtoa(-1));
 	}
-#endif /* CONFIG_PHYS_64BIT */
+#endif /* CONFIG_64BIT */
 
 	return 0;
 }