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x86: Add support for newer CAR schemes

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Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.

To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2019-12-06 21:42:25 -07:00 • committed by Bin Meng
parent 2e2a0035d4
commit f45e747d6d
5 changed files with 564 additions and 7 deletions
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12
arch/x86/include/asm/processor.h
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@ -25,8 +25,6 @@
/* Length of the public header on Intel microcode blobs */
#define UCODE_HEADER_LEN 0x30
#ifndef __ASSEMBLY__
/*
* This register is documented in (for example) the Intel Atom Processor E3800
* Product Family Datasheet in "PCU - Power Management Controller (PMC)".
@ -37,11 +35,11 @@
*/
#define IO_PORT_RESET 0xcf9
enum {
SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */
RST_CPU = 1 << 2, /* initiate reset */
FULL_RST = 1 << 3, /* full power cycle */
};
#define SYS_RST (1 << 1) /* 0 for soft reset, 1 for hard reset */
#define RST_CPU (1 << 2) /* initiate reset */
#define FULL_RST (1 << 3) /* full power cycle */
#ifndef __ASSEMBLY__
static inline __attribute__((always_inline)) void cpu_hlt(void)
{