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riscv: ae350: Fix XIP config boot failure

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The booting flow is SPL -> OpenSBI -> U-Boot.
The boot hart may change after OpenSBI and may not always be hart0,
so wrap the related branch instruction with M-MODE.

Current DTB setup for XIP is not valid.
There is no chance for CONFIG_SYS_FDT_BASE, the DTB address used
in XIP mode, to be returned. Fix this.

Fixes: 2e8d2f8843 ("riscv: Remove OF_PRIOR_STAGE from RISC-V boards")
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Leo Yu-Chi Liang 2022-06-01 10:01:49 +08:00
parent a5041e33e4
commit f4512618ca
2 changed files with 14 additions and 7 deletions
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2
arch/riscv/cpu/start.S
View file

@ -140,7 +140,9 @@ call_harts_early_init:
* accesses gd). * accesses gd).
*/ */
mv gp, s0 mv gp, s0
#if CONFIG_IS_ENABLED(RISCV_MMODE)
bnez tp, secondary_hart_loop bnez tp, secondary_hart_loop
#endif
#endif #endif
mv a0, s0 mv a0, s0

13
board/AndesTech/ax25-ae350/ax25-ae350.c
View file

@ -54,17 +54,22 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
return 0; return 0;
} }
#define ANDES_HW_DTB_ADDRESS 0xF2000000
void *board_fdt_blob_setup(int *err) void *board_fdt_blob_setup(int *err)
{ {
*err = 0; *err = 0;
#if defined(CONFIG_OF_BOARD)
if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
if (gd->arch.firmware_fdt_addr)
return (void *)(ulong)gd->arch.firmware_fdt_addr; return (void *)(ulong)gd->arch.firmware_fdt_addr;
#elif defined(CONFIG_OF_SEPARATE) }
if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC)
return (void *)CONFIG_SYS_FDT_BASE; return (void *)CONFIG_SYS_FDT_BASE;
#else return (void *)ANDES_HW_DTB_ADDRESS;
*err = -EINVAL; *err = -EINVAL;
return NULL; return NULL;
#endif
} }
int smc_init(void) int smc_init(void)