From 31cbcb5ddd2fd43c0895e0253550e314c6e132f7 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 5 Feb 2018 13:46:47 +0800 Subject: [PATCH 1/7] ARMv8: ls1046a: Enable PCIe and E1000 in lpuart defconfig Enable PCIe and E1000 in ls1046aqds lpuart defconfig. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- configs/ls1046aqds_lpuart_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index a9a073f201d..f1c6da9a734 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -18,6 +18,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -34,6 +35,12 @@ CONFIG_FSL_CAAM=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_SPI=y From ccd6849031bf19f0fc1af11bee9925db2ea415c7 Mon Sep 17 00:00:00 2001 From: Rajat Srivastava Date: Fri, 2 Feb 2018 17:52:07 +0530 Subject: [PATCH 2/7] armv8: ls1088a: qspi: Enable XIP mode above 16 MB addresses Currently in LS1088A, XIP mode in QSPI works up to 16 MB addresses. This patch enables QSPI support in XIP mode for addresses above 16 MB as well. Signed-off-by: Rajat Srivastava Reviewed-by: York Sun --- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088aqds_qspi_defconfig | 1 + configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_qspi_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index e464951ab6e..a234210726f 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1088AQDS=y CONFIG_SECURE_BOOT=y CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 1e368d7b6a5..f174b1e429f 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1088AQDS=y CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 19c76b6fe15..6f43a79cd85 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -32,6 +32,7 @@ CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_QSPI_AHB_INIT=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 8a0884621b5..58b697735dd 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -32,6 +32,7 @@ CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_QSPI_AHB_INIT=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y From 30cf7f818dfcb6bd33ecf8433f3ccf8392141e8d Mon Sep 17 00:00:00 2001 From: Sriram Dash Date: Tue, 30 Jan 2018 15:58:44 +0530 Subject: [PATCH 3/7] armv8: Remove dependency of SERDES for LSCH2 and LSCH3 Remove dependency of SYS_HAS_SERDES for Layerscape Chasis 2 and Layerscape Chasis 3. Signed-off-by: Sriram Dash Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index cefbdfe8556..7b59dc9a7c8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -3,6 +3,8 @@ config ARCH_LS1012A select ARMV8_SET_SMPEN select ARM_ERRATA_855873 select FSL_LSCH2 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES select SYS_FSL_DDR_BE select SYS_FSL_MMDC select SYS_FSL_ERRATUM_A010315 @@ -19,6 +21,8 @@ config ARCH_LS1043A select ARMV8_SET_SMPEN select ARM_ERRATA_855873 select FSL_LSCH2 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 @@ -45,6 +49,8 @@ config ARCH_LS1046A bool select ARMV8_SET_SMPEN select FSL_LSCH2 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 @@ -72,6 +78,8 @@ config ARCH_LS1088A select ARMV8_SET_SMPEN select ARM_ERRATA_855873 select FSL_LSCH3 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 @@ -105,6 +113,8 @@ config ARCH_LS2080A select ARM_ERRATA_829520 select ARM_ERRATA_833471 select FSL_LSCH3 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 @@ -142,13 +152,9 @@ config FSL_LSCH2 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_BE - select SYS_FSL_SRDS_1 - select SYS_HAS_SERDES config FSL_LSCH3 bool - select SYS_FSL_SRDS_1 - select SYS_HAS_SERDES config FSL_MC_ENET bool "Management Complex network" From c883f351e61f425f72d110375eaa80d5ecb5ee64 Mon Sep 17 00:00:00 2001 From: Vinitha Pillai-B57223 Date: Tue, 9 Jan 2018 23:03:42 +0530 Subject: [PATCH 4/7] armv8: ls1012ardb: Add distro secure boot support Enable validation of boot.scr script prior to its execution dependent on "secureboot" flag in environment. Enable fall back option to qspi boot in case of secure boot. Signed-off-by: Sumit Garg Signed-off-by: Vinitha Pillai Reviewed-by: York Sun --- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 13 ++++++------ include/configs/ls1012ardb.h | 20 +++++++++++++++++-- 2 files changed, 24 insertions(+), 9 deletions(-) diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index b6930be3381..0bec6b265f6 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -2,7 +2,9 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012ARDB=y CONFIG_SECURE_BOOT=y CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" +CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -12,7 +14,7 @@ CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" -CONFIG_HUSH_PARSER=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -20,16 +22,12 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +# CONFIG_BLK is not set +CONFIG_DM_MMC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y @@ -42,6 +40,7 @@ CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 438b5a63386..97ed9092e0a 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -63,16 +63,20 @@ "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ + "kernelheader_addr=0x800000\0" \ "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ "kernelheader_addr_r=0x80200000\0" \ "kernel_addr_r=0x81000000\0" \ "fdt_addr_r=0x90000000\0" \ "load_addr=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ "console=ttyS0,115200\0" \ BOOTENV \ "boot_scripts=ls1012ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1012ardb_bs.out\0" \ "scan_dev_for_boot_part=" \ "part list ${devtype} ${devnum} devplist; " \ "env exists devplist || setenv devplist 1; " \ @@ -90,15 +94,27 @@ "run scan_dev_for_scripts; " \ "done;" \ "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ "installer=load mmc 0:2 $load_addr " \ "/flex_installer_arm64.itb; " \ "bootm $load_addr#$board\0" \ "qspi_bootcmd=echo Trying load from qspi..;" \ "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size && bootm $load_addr#$board\0" + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" #undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" #include From dfaec76029f27ae6831babc0cdcf2816ee491f74 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Thu, 25 Jan 2018 14:11:17 +0100 Subject: [PATCH 5/7] crypto/fsl: instantiate all rng state handles Extend the instantiate_rng() function and the corresponding CAAM job descriptor to instantiate all RNG state handles. This moves the RNG instantiation code in line with the CAAM kernel driver. Previously, only the first state handle was instantiated. The second one was instantiated by the CAAM kernel driver. This works if the kernel runs in secure mode, but fails in non-secure mode since the kernel driver uses DEC0 directly instead of over the job ring interface. Instantiating all RNG state handles in u-boot removes the need for using DEC0 in the kernel driver, making it possible to use the CAAM in non-secure mode. Signed-off-by: Lukas Auer Tested-by: Bryan O'Donoghue Reviewed-by: York Sun --- drivers/crypto/fsl/jobdesc.c | 29 ++++++++++-------- drivers/crypto/fsl/jobdesc.h | 2 +- drivers/crypto/fsl/jr.c | 57 ++++++++++++++++++++++-------------- drivers/crypto/fsl/jr.h | 2 ++ include/fsl_sec.h | 3 ++ 5 files changed, 57 insertions(+), 36 deletions(-) diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index 375ff9d0e38..aadf8511014 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -257,7 +257,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, * Descriptor to instantiate RNG State Handle 0 in normal mode and * load the JDKEK, TDKEK and TDSK registers */ -void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc) +void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc, int handle) { u32 *jump_cmd; @@ -265,21 +265,24 @@ void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc) /* INIT RNG in non-test mode */ append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | - OP_ALG_AS_INIT); + (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT); - /* wait for done */ - jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); - set_jump_tgt_here(desc, jump_cmd); + /* For SH0, Secure Keys must be generated as well */ + if (handle == 0) { + /* wait for done */ + jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); + set_jump_tgt_here(desc, jump_cmd); - /* - * load 1 to clear written reg: - * resets the done interrrupt and returns the RNG to idle. - */ - append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); + /* + * load 1 to clear written reg: + * resets the done interrupt and returns the RNG to idle. + */ + append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); - /* generate secure keys (non-test) */ - append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | - OP_ALG_RNG4_SK); + /* generate secure keys (non-test) */ + append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | + OP_ALG_RNG4_SK); + } } /* Change key size to bytes form bits in calling function*/ diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h index 112404c74d6..75c9424c4a8 100644 --- a/drivers/crypto/fsl/jobdesc.h +++ b/drivers/crypto/fsl/jobdesc.h @@ -40,7 +40,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *enc_blob, uint8_t *plain_txt, uint32_t out_sz); -void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc); +void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc, int handle); void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, struct pk_in_params *pkin, uint8_t *out, diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index a05779826fe..34bd070426b 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -444,35 +444,49 @@ int sec_reset(void) #ifndef CONFIG_SPL_BUILD static int instantiate_rng(uint8_t sec_idx) { - struct result op; u32 *desc; u32 rdsta_val; - int ret = 0; + int ret = 0, sh_idx, size; ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; - memset(&op, 0, sizeof(struct result)); - desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6); if (!desc) { printf("cannot allocate RNG init descriptor memory\n"); return -1; } - inline_cnstr_jobdesc_rng_instantiation(desc); - int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN); - flush_dcache_range((unsigned long)desc, - (unsigned long)desc + size); + for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { + /* + * If the corresponding bit is set, this state handle + * was initialized by somebody else, so it's left alone. + */ + rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK; + if (rdsta_val & (1 << sh_idx)) + continue; - ret = run_descriptor_jr_idx(desc, sec_idx); + inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx); + size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + size); - if (ret) - printf("RNG: Instantiation failed with error %x\n", ret); + ret = run_descriptor_jr_idx(desc, sec_idx); - rdsta_val = sec_in32(&rng->rdsta); - if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED)) - return -1; + if (ret) + printf("RNG: Instantiation failed with error 0x%x\n", + ret); + + rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK; + if (!(rdsta_val & (1 << sh_idx))) { + free(desc); + return -1; + } + + memset(desc, 0, sizeof(uint32_t) * 6); + } + + free(desc); return ret; } @@ -524,14 +538,11 @@ static int rng_init(uint8_t sec_idx) ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; - - u32 rdsta = sec_in32(&rng->rdsta); - - /* Check if RNG state 0 handler is already instantiated */ - if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED) - return 0; + u32 inst_handles; do { + inst_handles = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK; + /* * If either of the SH's were instantiated by somebody else * then it is assumed that the entropy @@ -540,8 +551,10 @@ static int rng_init(uint8_t sec_idx) * Also, if a handle was instantiated, do not change * the TRNG parameters. */ - kick_trng(ent_delay, sec_idx); - ent_delay += 400; + if (!inst_handles) { + kick_trng(ent_delay, sec_idx); + ent_delay += 400; + } /* * if instantiate_rng(...) fails, the loop will rerun * and the kick_trng(...) function will modfiy the diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 8aab4c988da..ef515e74f8c 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -41,6 +41,8 @@ #define JQ_DEQ_TO_ERR -2 #define JQ_ENQ_ERR -3 +#define RNG4_MAX_HANDLES 2 + struct op_ring { phys_addr_t desc; uint32_t status; diff --git a/include/fsl_sec.h b/include/fsl_sec.h index a2f5f5a5f1a..4cbdb2d65a0 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -67,6 +67,9 @@ struct rng4tst { }; u32 rsvd1[40]; #define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001 +#define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002 +#define RNG_STATE_HANDLE_MASK \ + (RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED) u32 rdsta; /*RNG DRNG Status Register*/ u32 rsvd2[15]; }; From 990d06b0bcb0ad1d8a0d1846b2d4890db120364e Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Wed, 7 Feb 2018 10:01:56 +0800 Subject: [PATCH 6/7] PowerPC: phy: enable all phylib drivers when use phylib and tsec enet config_phylib_all_drivers.h should be included when CONFIG_PHYLIB and CONFIG_TSEC_ENET are defined. Fixes: 3146f0c017 ("Move PHYLIB to Kconfig") Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- arch/powerpc/include/asm/config.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 67e4b48a96a..39eeb39901d 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -70,11 +70,9 @@ #endif /* The TSEC driver uses the PHYLIB infrastructure */ -#ifndef CONFIG_PHYLIB -#if defined(CONFIG_TSEC_ENET) +#if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB) #include #endif /* TSEC_ENET */ -#endif /* !CONFIG_PHYLIB */ /* The FMAN driver uses the PHYLIB infrastructure */ From ee3556bcafbb05e59aabdc31368984e76acaabc4 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 7 Feb 2018 11:47:22 -0800 Subject: [PATCH 7/7] drivers/ddr/fsl: Dual-license DDR driver To make this driver easier to be reused, dual-license DDR driver. Signed-off-by: York Sun CC: Simon Glass CC: Tom Rini CC: Heinrich Schuchardt CC: Thomas Schaefer CC: Masahiro Yamada CC: Robert P. J. Day CC: Alexander Merkle CC: Joakim Tjernlund CC: Curt Brune CC: Valentin Longchamp CC: Wolfgang Denk CC: Anatolij Gustschin CC: Ira W. Snyder CC: Marek Vasut CC: Kyle Moffett CC: Sebastien Carlier CC: Stefan Roese CC: Peter Tyser CC: Paul Gortmaker CC: Peter Tyser CC: Jean-Christophe PLAGNIOL-VILLARD --- drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- drivers/ddr/fsl/ctrl_regs.c | 2 +- drivers/ddr/fsl/ddr1_dimm_params.c | 2 +- drivers/ddr/fsl/ddr2_dimm_params.c | 2 +- drivers/ddr/fsl/ddr3_dimm_params.c | 2 +- drivers/ddr/fsl/ddr4_dimm_params.c | 2 +- drivers/ddr/fsl/fsl_ddr_gen4.c | 2 +- drivers/ddr/fsl/fsl_mmdc.c | 2 +- drivers/ddr/fsl/interactive.c | 2 +- drivers/ddr/fsl/lc_common_dimm_params.c | 2 +- drivers/ddr/fsl/main.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen2.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 2 +- drivers/ddr/fsl/mpc86xx_ddr.c | 2 +- drivers/ddr/fsl/options.c | 2 +- drivers/ddr/fsl/util.c | 2 +- include/common_timing_params.h | 2 +- include/fsl_ddr.h | 2 +- include/fsl_ddr_dimm_params.h | 2 +- include/fsl_ddrc_version.h | 2 +- include/fsl_immap.h | 2 +- include/fsl_mmdc.h | 2 +- 23 files changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index aaf4dfb1e79..4fa0d5d4e41 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -1,7 +1,7 @@ /* * Copyright 2013 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause * * Derived from mpc85xx_ddr_gen3.c, removed all workarounds */ diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 8b8727116da..73083090e4e 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -2,7 +2,7 @@ * Copyright 2008-2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause */ /* diff --git a/drivers/ddr/fsl/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c index c02725e6114..8a8c17cae9e 100644 --- a/drivers/ddr/fsl/ddr1_dimm_params.c +++ b/drivers/ddr/fsl/ddr1_dimm_params.c @@ -1,7 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ #include diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c index 062c8490753..3ff35aa5c91 100644 --- a/drivers/ddr/fsl/ddr2_dimm_params.c +++ b/drivers/ddr/fsl/ddr2_dimm_params.c @@ -1,7 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ #include diff --git a/drivers/ddr/fsl/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c index 8a0587a6462..d8f170e605c 100644 --- a/drivers/ddr/fsl/ddr3_dimm_params.c +++ b/drivers/ddr/fsl/ddr3_dimm_params.c @@ -6,7 +6,7 @@ * from ddr3 spd, please refer to the spec * JEDEC standard No.21-C 4_01_02_11R18.pdf * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ #include diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c index 4867fbc932b..343b0ff8666 100644 --- a/drivers/ddr/fsl/ddr4_dimm_params.c +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -2,7 +2,7 @@ * Copyright 2014-2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause * * calculate the organization and timing parameter * from ddr3 spd, please refer to the spec diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index c225c8e723e..1829aa4fa45 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -1,7 +1,7 @@ /* * Copyright 2014-2015 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause */ #include diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c index 52eec0f9e99..1312c081c5d 100644 --- a/drivers/ddr/fsl/fsl_mmdc.c +++ b/drivers/ddr/fsl/fsl_mmdc.c @@ -1,7 +1,7 @@ /* * Copyright 2016 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause */ /* diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index 1fa35c3c427..f5c21e44685 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -2,7 +2,7 @@ * Copyright 2010-2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause */ /* diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index 6599901893d..3d28abda542 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -2,7 +2,7 @@ * Copyright 2008-2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP Semiconductor * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ #include diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index d0a7b3f1076..85897b16b65 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -1,7 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ /* diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index c005f5294cb..f74bf32c647 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -1,7 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ #include diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c index 898b0cd33cd..6da4400566b 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -1,7 +1,7 @@ /* * Copyright 2008-2011 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ #include diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index afbed598c8d..e58f76ae65f 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -1,7 +1,7 @@ /* * Copyright 2008-2012 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ #include diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c index a65eb3144fc..bda5b83df5c 100644 --- a/drivers/ddr/fsl/mpc86xx_ddr.c +++ b/drivers/ddr/fsl/mpc86xx_ddr.c @@ -1,7 +1,7 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ #include diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 85ec48c28e3..1abea1dfed0 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -2,7 +2,7 @@ * Copyright 2008, 2010-2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause */ #include diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index d6e6e78de32..11731cb9b9d 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -1,7 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ #include diff --git a/include/common_timing_params.h b/include/common_timing_params.h index 070010728b8..3881456a96f 100644 --- a/include/common_timing_params.h +++ b/include/common_timing_params.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ #ifndef COMMON_TIMING_PARAMS_H diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 261b94e9845..996723c636a 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ #ifndef FSL_DDR_MAIN_H diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h index 1632a8fd366..af673fd3405 100644 --- a/include/fsl_ddr_dimm_params.h +++ b/include/fsl_ddr_dimm_params.h @@ -2,7 +2,7 @@ * Copyright 2008-2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP Semiconductor * - * SPDX-License-Identifier: GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 BSD-3-Clause */ #ifndef DDR2_DIMM_PARAMS_H diff --git a/include/fsl_ddrc_version.h b/include/fsl_ddrc_version.h index 60ba98bf810..4c5aed474c4 100644 --- a/include/fsl_ddrc_version.h +++ b/include/fsl_ddrc_version.h @@ -1,7 +1,7 @@ /* * Copyright 2014 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause */ #ifndef __FSL_DDRC_VER_H diff --git a/include/fsl_immap.h b/include/fsl_immap.h index 4f5a19cdc1a..e210c4c472e 100644 --- a/include/fsl_immap.h +++ b/include/fsl_immap.h @@ -3,7 +3,7 @@ * * Copyright 2013-2014 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause */ #ifndef __FSL_IMMAP_H diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h index d5c4f8d59a7..d364e075193 100644 --- a/include/fsl_mmdc.h +++ b/include/fsl_mmdc.h @@ -1,7 +1,7 @@ /* * Copyright 2016 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause */ #ifndef FSL_MMDC_H