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ARM: add relocation support

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!! This breaks support for all arm boards !!

To compile in old style, you must define
CONFIG_SYS_ARM_WITHOUT_RELOC or you can compile
with "CONFIG_SYS_ARM_WITHOUT_RELOC=1 ./MAKEALL board"

!! This define will be removed soon, so convert your
board to use relocation support

Portions of this work were supported by funding from
the CE Linux Forum.

Signed-off-by: Heiko Schocher <hs@denx.de>

Fix boot from NAND for non-ARM systems
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Heiko Schocher 2010-09-17 13:10:39 +02:00 • committed by Wolfgang Denk
parent 4fff329df2
commit f1d2b313c9
13 changed files with 910 additions and 8 deletions
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37
arch/arm/lib/cache-cp15.c
View file

@ -44,17 +44,44 @@ static void cp_delay (void)
asm volatile("" : : : "memory");
}
/* to activate the MMU we need to set up virtual memory: use 1M areas in bss */
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
static inline void dram_bank_mmu_setup(int bank)
{
u32 *page_table = (u32 *)gd->tlb_addr;
bd_t *bd = gd->bd;
int i;
debug("%s: bank: %d\n", __func__, bank);
for (i = bd->bi_dram[bank].start >> 20;
i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
i++) {
page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
}
}
#endif
/* to activate the MMU we need to set up virtual memory: use 1M areas */
static inline void mmu_setup(void)
{
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
u32 *page_table = (u32 *)gd->tlb_addr;
#else
static u32 __attribute__((aligned(16384))) page_table[4096];
bd_t *bd = gd->bd;
int i, j;
int j;
#endif
int i;
u32 reg;
/* Set up an identity-mapping for all 4GB, rw for everyone */
for (i = 0; i < 4096; i++)
page_table[i] = i << 20 | (3 << 10) | 0x12;
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
dram_bank_mmu_setup(i);
}
#else
/* Then, enable cacheable and bufferable for RAM only */
for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) {
for (i = bd->bi_dram[j].start >> 20;
@ -63,6 +90,7 @@ static inline void mmu_setup(void)
page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
}
}
#endif
/* Copy the page table address to cp15 */
asm volatile("mcr p15, 0, %0, c2, c0, 0"
@ -74,7 +102,6 @@ static inline void mmu_setup(void)
reg = get_cr(); /* get control reg. */
cp_delay();
set_cr(reg | CR_M);
}
/* cache_bit must be either CR_I or CR_C */
@ -96,6 +123,10 @@ static void cache_disable(uint32_t cache_bit)
uint32_t reg;
if (cache_bit == CR_C) {
/* if cache isn;t enabled no need to disable */
reg = get_cr();
if ((reg & CR_C) != CR_C)
return;
/* if disabling data cache, disable mmu too */
cache_bit |= CR_M;
flush_cache(0, ~0);