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arm: usb: dra7xx: xHCI registers based on USB port index
Modify the determination of the base address of xHCI registers of DRA7XX targets. Before the commit: by the target. After the commit: by the USB port index. Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Roger Quadros <rogerq@ti.com> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Roger Quadros <rogerq@ti.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
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parent
67566ab66b
commit
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4 changed files with 15 additions and 2 deletions
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@ -91,6 +91,7 @@ CONFIG_OMAP_TIMER=y
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CONFIG_USB=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_XHCI_DRA7XX_INDEX=1
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_GADGET=y
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CONFIG_USB_DWC3_GADGET=y
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CONFIG_USB_DWC3_OMAP=y
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CONFIG_USB_DWC3_OMAP=y
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@ -96,6 +96,7 @@ CONFIG_OMAP_TIMER=y
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CONFIG_USB=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_XHCI_DRA7XX_INDEX=1
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_GADGET=y
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CONFIG_USB_DWC3_GADGET=y
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CONFIG_USB_DWC3_OMAP=y
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CONFIG_USB_DWC3_OMAP=y
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@ -44,6 +44,15 @@ config USB_XHCI_ZYNQMP
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help
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help
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Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs.
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Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs.
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config USB_XHCI_DRA7XX_INDEX
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int "DRA7XX xHCI USB index"
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range 0 1
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default 0
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depends on DRA7XX
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help
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Select the DRA7XX xHCI USB index.
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Current supported values: 0, 1.
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endif # USB_XHCI_HCD
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endif # USB_XHCI_HCD
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config USB_EHCI_HCD
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config USB_EHCI_HCD
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@ -10,14 +10,16 @@
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#ifndef _ASM_ARCH_XHCI_OMAP_H_
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#ifndef _ASM_ARCH_XHCI_OMAP_H_
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#define _ASM_ARCH_XHCI_OMAP_H_
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#define _ASM_ARCH_XHCI_OMAP_H_
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#ifdef CONFIG_TARGET_DRA7XX_EVM
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#ifdef CONFIG_DRA7XX
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#if CONFIG_USB_XHCI_DRA7XX_INDEX == 1
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#define OMAP_XHCI_BASE 0x488d0000
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#define OMAP_XHCI_BASE 0x488d0000
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#define OMAP_OCP1_SCP_BASE 0x4A081000
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#define OMAP_OCP1_SCP_BASE 0x4A081000
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#define OMAP_OTG_WRAPPER_BASE 0x488c0000
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#define OMAP_OTG_WRAPPER_BASE 0x488c0000
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#elif defined CONFIG_TARGET_AM57XX_EVM
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#elif CONFIG_USB_XHCI_DRA7XX_INDEX == 0
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#define OMAP_XHCI_BASE 0x48890000
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#define OMAP_XHCI_BASE 0x48890000
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#define OMAP_OCP1_SCP_BASE 0x4A084c00
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#define OMAP_OCP1_SCP_BASE 0x4A084c00
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#define OMAP_OTG_WRAPPER_BASE 0x48880000
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#define OMAP_OTG_WRAPPER_BASE 0x48880000
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#endif /* CONFIG_USB_XHCI_DRA7XX_INDEX == 1 */
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#elif defined CONFIG_AM43XX
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#elif defined CONFIG_AM43XX
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#define OMAP_XHCI_BASE 0x483d0000
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#define OMAP_XHCI_BASE 0x483d0000
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#define OMAP_OCP1_SCP_BASE 0x483E8000
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#define OMAP_OCP1_SCP_BASE 0x483E8000
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