Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-05-09 03:21:51 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

ls102xa: etsec: Use proper settings for BE BDs

Browse source 
Replace the DMACTRL[LE] hack with recommended settings
for ETSECDMAMCR to get the same end effect - obtaining
big-endian buffer descriptors and frame data for eTSEC.
The reset / default value for ETSECDMAMCR is preserved,
excepting the BD and FR bits which are cleared to enable
the BE mode in accordance with the H/W specifications.

Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA"
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Claudiu Manoil 2015-08-12 13:29:14 +03:00 • committed by York Sun
parent da2919b4a9
commit ebe4c1e646
4 changed files with 5 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

6
drivers/net/tsec.c
View file

@ -271,9 +271,6 @@ void redundant_init(struct eth_device *dev)
out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
#ifdef CONFIG_LS102XA
setbits_be32(&regs->dmactrl, DMACTRL_LE);
#endif
do {
uint16_t status;
@ -370,9 +367,6 @@ static void startup_tsec(struct eth_device *dev)
out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
#ifdef CONFIG_LS102XA
setbits_be32(&regs->dmactrl, DMACTRL_LE);
#endif
}
/* This returns the status bits of the device. The return value