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arm: dra7xx: clock: Add the dplls data

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A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
Lokesh Vutla 2013-02-12 21:29:05 +00:00 • committed by Tom Rini
parent d4e4129c31
commit ea8eff1fe0
4 changed files with 94 additions and 8 deletions
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3
arch/arm/include/asm/omap_common.h
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@ -27,7 +27,7 @@
#include <common.h>
#define NUM_SYS_CLKS 7
#define NUM_SYS_CLKS 8
struct prcm_regs {
/* cm1.ckgen */
@ -473,6 +473,7 @@ struct dplls {
const struct dpll_params *abe;
const struct dpll_params *iva;
const struct dpll_params *usb;
const struct dpll_params *ddr;
};
struct pmic_data {