Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-04-17 10:24:49 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

- simplify the STM32MP15x package parsing code

Browse source 
- remove test on CONFIG_DM_REGULATOR in stm32mp1 board
   and enable CONFIG_DM_REGULATOR for stm32f769-disco
 - handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start'
   after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>)
 - Fix SYS_HZ_CLOCK value for stih410-b2260 board
 - Switch STMM32MP15x DHSOM to FMC2 EBI driver
 - Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAmMZoW4ACgkQ4rK92eCq
 k3W2MAgAsmy2aSlMYo/AGlJ/KCrZuk6OirNHtdOdacvbcdUUbpkNpBSjdkrRm2If
 VUnY1utIIJe6gFgnBUxXJ3RF5FZuhkdawc6V25HtDp6H3WamzJknKs5Vc4TlKp59
 hZCOto7/+G/cd2XLdCKFUBl+new1pdDPsEm56+57DeZ7QGAQRX35PUQ5+HBjQJ/N
 n/wJgS6wkEdIQLLwmCVxbHUkC+pRotTza5F2A0qZJgYPMcMpVFYKtzIa4GbWB5YS
 MKGHbM8f3C8RLPQaHHTRycoA2Yor1I52B4Oi7605c5zHQr9pjrgtWsernDzkIhsB
 ThYHSYQBUBTY4HBfzFwzCkVGqqLWNg==
 =PMFY
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20220907' of https://source.denx.de/u-boot/custodians/u-boot-stm

- simplify the STM32MP15x package parsing code
- remove test on CONFIG_DM_REGULATOR in stm32mp1 board
  and enable CONFIG_DM_REGULATOR for stm32f769-disco
- handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start'
  after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>)
- Fix SYS_HZ_CLOCK value for stih410-b2260 board
- Switch STMM32MP15x DHSOM to FMC2 EBI driver
- Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel
This commit is contained in:
Tom Rini 2022-09-08 08:33:41 -04:00
commit e9de8c8c64
15 changed files with 158 additions and 155 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/dts/stm32f746-disco-u-boot.dtsi
View file

@ -58,7 +58,7 @@
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};

2
arch/arm/dts/stm32mp151.dtsi
View file

@ -1663,7 +1663,6 @@
ranges = <0 0x50002000 0xa400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
hwlocks = <&hwspinlock 0>;
pins-are-numbered;
gpioa: gpio@50002000 {
@ -1796,7 +1795,6 @@
pins-are-numbered;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
hwlocks = <&hwspinlock 0>;
gpioz: gpio@54004000 {
gpio-controller;

8
arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi
View file

@ -5,14 +5,6 @@
#include "stm32mp15xx-dhcom-u-boot.dtsi"
/ {
aliases {
/delete-property/ ethernet1;
};
};
/delete-node/ &ks8851;
&usbotg_hs {
dr_mode = "peripheral";
};

14
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
View file

@ -9,8 +9,6 @@
#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
/delete-node/ &ksz8851;
/ {
aliases {
i2c1 = &i2c2;
@ -21,7 +19,6 @@
spi0 = &qspi;
usb0 = &usbotg_hs;
eeprom0 = &eeprom0;
ethernet1 = &ks8851;
};
config {
@ -30,12 +27,6 @@
dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
};
/* This is actually on FMC2, but we do not have bus driver for that */
ks8851: ks8851mll@64000000 {
compatible = "micrel,ks8851-mll";
reg = <0x64000000 0x20000>;
};
};
&ethernet0 {
@ -74,11 +65,6 @@
};
&pinctrl {
/* These should bound to FMC2 bus driver, but we do not have one */
pinctrl-0 = <&fmc_pins_b &mco2_pins_a>;
pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>;
pinctrl-names = "default", "sleep";
mco2_pins_a: mco2-0 {
pins {
pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */

16
arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi
View file

@ -5,25 +5,16 @@
#include "stm32mp15xx-dhcor-u-boot.dtsi"
/delete-node/ &ksz8851;
/ {
aliases {
mmc0 = &sdmmc1;
mmc1 = &sdmmc2;
usb0 = &usbotg_hs;
ethernet1 = &ks8851;
};
config {
dh,board-coding-gpios = <&gpioh 9 0>, <&gpioh 8 0>, <&gpioh 3 0>;
};
/* This is actually on FMC2, but we do not have bus driver for that */
ks8851: ks8851mll@64000000 {
compatible = "micrel,ks8851-mll";
reg = <0x64000000 0x20000>;
};
};
&ethernet0 {
@ -38,13 +29,6 @@
};
};
&pinctrl {
/* These should bound to FMC2 bus driver, but we do not have one */
pinctrl-0 = <&fmc_pins_b>;
pinctrl-1 = <&fmc_sleep_pins_b>;
pinctrl-names = "default", "sleep";
};
&sdmmc1 {
u-boot,dm-spl;
st,use-ckin;

15
arch/arm/mach-stm32mp/stm32mp15x.c
View file

@ -274,7 +274,6 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
u32 cpu_type = get_cpu_type();
u32 ct = cpu_type & ~(BIT(7) | BIT(0));
u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0));
u32 cp = get_cpu_package();
/* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */
switch (ct) {
@ -293,17 +292,9 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
}
/* Package */
switch (cp) {
case STM32MP15_PKG_AA_LBGA448:
case STM32MP15_PKG_AB_LBGA354:
case STM32MP15_PKG_AC_TFBGA361:
case STM32MP15_PKG_AD_TFBGA257:
*pkg = cp;
break;
default:
*pkg = 0;
break;
}
*pkg = get_cpu_package();
if (*pkg > STM32MP15_PKG_AA_LBGA448)
*pkg = STM32MP15_PKG_UNKNOWN;
/* Revision */
switch (get_cpu_rev()) {

52
board/dhelectronics/dh_stm32mp1/board.c
View file

@ -527,56 +527,6 @@ static void sysconf_init(void)
#endif
}
static void board_init_fmc2(void)
{
#define STM32_FMC2_BCR1 0x0
#define STM32_FMC2_BTR1 0x4
#define STM32_FMC2_BWTR1 0x104
#define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
#define STM32_FMC2_BCRx_FMCEN BIT(31)
#define STM32_FMC2_BCRx_WREN BIT(12)
#define STM32_FMC2_BCRx_RSVD BIT(7)
#define STM32_FMC2_BCRx_FACCEN BIT(6)
#define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
#define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
#define STM32_FMC2_BCRx_MUXEN BIT(1)
#define STM32_FMC2_BCRx_MBKEN BIT(0)
#define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
#define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
#define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
#define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
#define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
#define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
#define RCC_MP_AHB6RSTCLRR 0x218
#define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
#define RCC_MP_AHB6ENSETR 0x19c
#define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
STM32_FMC2_BCRx_MBKEN;
const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
STM32_FMC2_BTRx_BUSTURN(2) |
STM32_FMC2_BTRx_DATAST(0x22) |
STM32_FMC2_BTRx_ADDHLD(2) |
STM32_FMC2_BTRx_ADDSET(2);
/* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
/* KS8851-16MLL -- Muxed mode */
writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
/* AS7C34098 SRAM on X11 -- Muxed mode */
writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
}
#ifdef CONFIG_DM_REGULATOR
#define STPMIC_NVM_BUCKS_VOUT_SHR 0xfc
#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V2 0
@ -671,8 +621,6 @@ int board_init(void)
sysconf_init();
board_init_fmc2();
return 0;
}

8
board/st/stm32mp1/stm32mp1.c
View file

@ -494,7 +494,7 @@ static void sysconf_init(void)
ret = uclass_get_device_by_driver(UCLASS_PMIC,
DM_DRIVER_GET(stm32mp_pwr_pmic),
&pwr_dev);
if (!ret && IS_ENABLED(CONFIG_DM_REGULATOR)) {
if (!ret) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(stm32mp_bsec),
&dev);
@ -555,9 +555,6 @@ static int board_stm32mp15x_dk2_init(void)
struct gpio_desc hdmi, audio;
int ret = 0;
if (!IS_ENABLED(CONFIG_DM_REGULATOR))
return -ENODEV;
/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
if (!ofnode_valid(node)) {
@ -658,8 +655,7 @@ int board_init(void)
if (board_is_stm32mp15x_dk2())
board_stm32mp15x_dk2_init();
if (IS_ENABLED(CONFIG_DM_REGULATOR))
regulators_enable_boot_on(_DEBUG);
regulators_enable_boot_on(_DEBUG);
/*
* sysconf initialisation done only when U-Boot is running in secure

1
configs/stm32f769-disco_defconfig
View file

@ -50,6 +50,7 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_DW_ALTDESCRIPTOR=y
CONFIG_MII=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_DM_REGULATOR=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y

1
configs/stm32f769-disco_spl_defconfig
View file

@ -71,6 +71,7 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_DW_ALTDESCRIPTOR=y
CONFIG_MII=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_DM_REGULATOR=y
CONFIG_SPL_PINCTRL=y
CONFIG_SPL_RAM=y
CONFIG_SPECIFY_CONSOLE_INDEX=y

1
configs/stm32mp15_dhcom_basic_defconfig
View file

@ -108,6 +108,7 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_STM32_FMC2_EBI=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y

1
configs/stm32mp15_dhcor_basic_defconfig
View file

@ -105,6 +105,7 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_STM32_FMC2_EBI=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_SUPPORT_EMMC_BOOT=y

35
drivers/clk/stm32/clk-stm32mp1.c
View file

@ -962,6 +962,24 @@ static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
return dfout;
}
static ulong stm32mp1_clk_get_by_name(const char *name)
{
struct clk clk;
struct udevice *dev = NULL;
ulong clock = 0;
if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
if (clk_request(dev, &clk)) {
log_err("%s request", name);
} else {
clk.id = 0;
clock = clk_get_rate(&clk);
}
}
return clock;
}
static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
{
u32 reg;
@ -1127,24 +1145,11 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
break;
/* other */
case _USB_PHY_48:
clock = 48000000;
clock = stm32mp1_clk_get_by_name("ck_usbo_48m");
break;
case _DSI_PHY:
{
struct clk clk;
struct udevice *dev = NULL;
if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
&dev)) {
if (clk_request(dev, &clk)) {
log_err("ck_dsi_phy request");
} else {
clk.id = 0;
clock = clk_get_rate(&clk);
}
}
clock = stm32mp1_clk_get_by_name("ck_dsi_phy");
break;
}
default:
break;
}

155
drivers/phy/phy-stm32-usbphyc.c
View file

@ -7,6 +7,7 @@
#include <common.h>
#include <clk.h>
#include <clk-uclass.h>
#include <div64.h>
#include <dm.h>
#include <fdtdec.h>
@ -17,6 +18,7 @@
#include <usb.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <dm/of_access.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
@ -72,6 +74,9 @@
#define PLL_INFF_MIN_RATE 19200000 /* in Hz */
#define PLL_INFF_MAX_RATE 38400000 /* in Hz */
/* USBPHYC_CLK48 */
#define USBPHYC_CLK48_FREQ 48000000 /* in Hz */
enum boosting_vals {
BOOST_1000_UA = 1000,
BOOST_2000_UA = 2000,
@ -144,6 +149,7 @@ struct stm32_usbphyc {
bool init;
bool powered;
} phys[MAX_PHYS];
int n_pll_cons;
};
static void stm32_usbphyc_get_pll_params(u32 clk_rate,
@ -203,18 +209,6 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
return 0;
}
static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
{
int i;
for (i = 0; i < MAX_PHYS; i++) {
if (usbphyc->phys[i].init)
return true;
}
return false;
}
static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
{
int i;
@ -227,18 +221,17 @@ static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
return false;
}
static int stm32_usbphyc_phy_init(struct phy *phy)
static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
{
struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
true : false;
int ret;
dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
/* Check if one phy port has already configured the pll */
if (pllen && stm32_usbphyc_is_init(usbphyc))
goto initialized;
/* Check if one consumer has already configured the pll */
if (pllen && usbphyc->n_pll_cons) {
usbphyc->n_pll_cons++;
return 0;
}
if (usbphyc->vdda1v1) {
ret = regulator_set_enable(usbphyc->vdda1v1, true);
@ -269,23 +262,19 @@ static int stm32_usbphyc_phy_init(struct phy *phy)
if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
return -EIO;
initialized:
usbphyc_phy->init = true;
usbphyc->n_pll_cons++;
return 0;
}
static int stm32_usbphyc_phy_exit(struct phy *phy)
static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
{
struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
usbphyc_phy->init = false;
usbphyc->n_pll_cons--;
/* Check if other phy port requires pllen */
if (stm32_usbphyc_is_init(usbphyc))
/* Check if other consumer requires pllen */
if (usbphyc->n_pll_cons)
return 0;
clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
@ -314,6 +303,42 @@ static int stm32_usbphyc_phy_exit(struct phy *phy)
return 0;
}
static int stm32_usbphyc_phy_init(struct phy *phy)
{
struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
if (usbphyc_phy->init)
return 0;
ret = stm32_usbphyc_pll_enable(usbphyc);
if (ret)
return log_ret(ret);
usbphyc_phy->init = true;
return 0;
}
static int stm32_usbphyc_phy_exit(struct phy *phy)
{
struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
if (!usbphyc_phy->init)
return 0;
ret = stm32_usbphyc_pll_disable(usbphyc);
usbphyc_phy->init = false;
return log_ret(ret);
}
static int stm32_usbphyc_phy_power_on(struct phy *phy)
{
struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
@ -498,6 +523,16 @@ static const struct phy_ops stm32_usbphyc_phy_ops = {
.of_xlate = stm32_usbphyc_of_xlate,
};
static int stm32_usbphyc_bind(struct udevice *dev)
{
int ret;
ret = device_bind_driver_to_node(dev, "stm32-usbphyc-clk", "ck_usbo_48m",
dev_ofnode(dev), NULL);
return log_ret(ret);
}
static int stm32_usbphyc_probe(struct udevice *dev)
{
struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
@ -591,6 +626,70 @@ U_BOOT_DRIVER(stm32_usb_phyc) = {
.id = UCLASS_PHY,
.of_match = stm32_usbphyc_of_match,
.ops = &stm32_usbphyc_phy_ops,
.bind = stm32_usbphyc_bind,
.probe = stm32_usbphyc_probe,
.priv_auto = sizeof(struct stm32_usbphyc),
};
struct stm32_usbphyc_clk {
bool enable;
};
static ulong stm32_usbphyc_clk48_get_rate(struct clk *clk)
{
return USBPHYC_CLK48_FREQ;
}
static int stm32_usbphyc_clk48_enable(struct clk *clk)
{
struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev);
struct stm32_usbphyc *usbphyc;
int ret;
if (usbphyc_clk->enable)
return 0;
usbphyc = dev_get_priv(clk->dev->parent);
/* ck_usbo_48m is generated by usbphyc PLL */
ret = stm32_usbphyc_pll_enable(usbphyc);
if (ret)
return ret;
usbphyc_clk->enable = true;
return 0;
}
static int stm32_usbphyc_clk48_disable(struct clk *clk)
{
struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev);
struct stm32_usbphyc *usbphyc;
int ret;
if (!usbphyc_clk->enable)
return 0;
usbphyc = dev_get_priv(clk->dev->parent);
ret = stm32_usbphyc_pll_disable(usbphyc);
if (ret)
return ret;
usbphyc_clk->enable = false;
return 0;
}
const struct clk_ops usbphyc_clk48_ops = {
.get_rate = stm32_usbphyc_clk48_get_rate,
.enable = stm32_usbphyc_clk48_enable,
.disable = stm32_usbphyc_clk48_disable,
};
U_BOOT_DRIVER(stm32_usb_phyc_clk) = {
.name = "stm32-usbphyc-clk",
.id = UCLASS_CLK,
.ops = &usbphyc_clk48_ops,
.priv_auto = sizeof(struct stm32_usbphyc_clk),
};

2
include/configs/stih410-b2260.h
View file

@ -14,7 +14,7 @@
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_1_SIZE 0x3E000000
#define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */
#define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */
/* Environment */