Merge branch 'master' into next

Signed-off-by: Tom Rini <trini@konsulko.com>

.github/pull_request_template.md

@@ -1,6 +1,6 @@
 Please do not submit a Pull Request via github.  Our project makes use of
 mailing lists for patch submission and review.  For more details please
-see https://www.denx.de/wiki/U-Boot/Patches
+see https://u-boot.readthedocs.io/en/latest/develop/sending_patches.html
 
 The only exception to this is in order to trigger a CI loop on Azure prior
 to posting of patches.

.gitlab-ci.yml

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-# Grab our configured image.  The source for this is found at:
+# Grab our configured image.  The source for this is found
-# https://source.denx.de/u-boot/gitlab-ci-runner
+# in the u-boot tree at tools/docker/Dockerfile
 image: trini/u-boot-gitlab-ci-runner:jammy-20220801-09Aug2022
 
 # We run some tests in different order, to catch some failures quicker.

Kconfig

@@ -299,7 +299,7 @@ config SYS_MALLOC_F_LEN
 	default 0x4000 if SANDBOX || RISCV || ARCH_APPLE || ROCKCHIP_RK3368 || \
 			  ROCKCHIP_RK3399
 	default 0x8000 if RCAR_GEN3
-	default 0x10000 if ARCH_IMX8 || (ARCH_IMX8M && !IMX8MQ)
+	default 0x10000 if ARCH_IMX8 || ARCH_IMX8M
 	default 0x2000
 	help
 	  Before relocation, memory is very limited on many platforms. Still,
@@ -325,6 +325,7 @@ config SPL_SYS_MALLOC_F_LEN
 	depends on SYS_MALLOC_F && SPL
 	default 0 if !SPL_FRAMEWORK
 	default 0x2800 if RCAR_GEN3
+	default 0x2000 if IMX8MQ
 	default SYS_MALLOC_F_LEN
 	help
 	  In SPL memory is very limited on many platforms. Still,

MAINTAINERS

@@ -264,6 +264,7 @@ F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
 F:	arch/arm/include/asm/mach-imx/
 F:	board/freescale/*mx*/
+F:	drivers/serial/serial_mxc.c
 
 ARM HISILICON
 M:	Peter Griffin <peter.griffin@linaro.org>

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2022
 PATCHLEVEL = 10
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc5
 NAME =
 
 # *DOCUMENTATION*
@@ -1004,22 +1004,12 @@ ifeq ($(CONFIG_INIT_SP_RELATIVE)$(CONFIG_OF_SEPARATE),yy)
 INPUTS-y += init_sp_bss_offset_check
 endif
 
-ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+ifeq ($(CONFIG_ARCH_ROCKCHIP)$(CONFIG_SPL),yy)
-INPUTS-y += u-boot-with-dtb.bin
+# Binman image dependencies
-endif
-
-ifeq ($(CONFIG_ARCH_ROCKCHIP),y)
-# On ARM64 this target is produced by binman so we don't need this dep
 ifeq ($(CONFIG_ARM64),y)
-ifeq ($(CONFIG_SPL),y)
+INPUTS-y += u-boot.itb
-# TODO: Get binman to generate this too
-INPUTS-y += u-boot-rockchip.bin
-endif
 else
-ifeq ($(CONFIG_SPL),y)
+INPUTS-y += u-boot.img
-# Generate these inputs for binman which will create the output files
-INPUTS-y += idbloader.img u-boot.img
-endif
 endif
 endif
 
@@ -1230,9 +1220,12 @@ else ifeq ($(CONFIG_OF_SEPARATE).$(CONFIG_OF_OMIT_DTB),y.)
 u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
 	$(call if_changed,cat)
 
+ifneq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR)$(CONFIG_OF_SEPARATE),yy)
 u-boot.bin: u-boot-dtb.bin FORCE
 	$(call if_changed,copy)
-else
+endif
+
+else ifneq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR)$(CONFIG_OF_SEPARATE),yy)
 u-boot.bin: u-boot-nodtb.bin FORCE
 	$(call if_changed,copy)
 endif
@@ -1280,7 +1273,7 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
 
 OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
 		$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
-		$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_EMBED),,-R .bootpg -R .resetvec))
+		$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_SEPARATE),-R .bootpg -R .resetvec))
 
 binary_size_check: u-boot-nodtb.bin FORCE
 	@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
@@ -1445,11 +1438,7 @@ MKIMAGEFLAGS_u-boot-spl.kwb = -n $(KWD_CONFIG_FILE) \
 MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -A $(ARCH) -T pblimage
 
-ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
-UBOOT_BIN := u-boot-with-dtb.bin
-else
 UBOOT_BIN := u-boot.bin
-endif
 
 MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
@@ -1505,29 +1494,6 @@ OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \
 u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE
 	$(call if_changed,pad_cat)
 
-ifeq ($(CONFIG_ARCH_ROCKCHIP),y)
-
-# TPL + SPL
-ifeq ($(CONFIG_SPL)$(CONFIG_TPL),yy)
-MKIMAGEFLAGS_u-boot-tpl-rockchip.bin = -n $(CONFIG_SYS_SOC) -T rksd
-tpl/u-boot-tpl-rockchip.bin: tpl/u-boot-tpl.bin FORCE
-	$(call if_changed,mkimage)
-idbloader.img: tpl/u-boot-tpl-rockchip.bin spl/u-boot-spl.bin FORCE
-	$(call if_changed,cat)
-else
-MKIMAGEFLAGS_idbloader.img = -n $(CONFIG_SYS_SOC) -T rksd
-idbloader.img: spl/u-boot-spl.bin FORCE
-	$(call if_changed,mkimage)
-endif
-
-ifeq ($(CONFIG_ARM64),y)
-OBJCOPYFLAGS_u-boot-rockchip.bin = -I binary -O binary \
-	--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
-u-boot-rockchip.bin: idbloader.img u-boot.itb FORCE
-	$(call if_changed,pad_cat)
-endif # CONFIG_ARM64
-
-endif # CONFIG_ARCH_ROCKCHIP
 
 ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy)
 MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE)
@@ -1639,17 +1605,14 @@ u-boot-with-nand-spl.sfp: u-boot-spl-padx4.sfp u-boot.img FORCE
 
 endif
 
-ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+ifeq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR)$(CONFIG_OF_SEPARATE),yy)
-u-boot-with-dtb.bin: u-boot.bin u-boot.dtb \
+u-boot.bin: u-boot-nodtb.bin u-boot.dtb u-boot-br.bin FORCE
-	$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR), u-boot-br.bin) FORCE
 	$(call if_changed,binman)
 
-ifeq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR),y)
 OBJCOPYFLAGS_u-boot-br.bin := -O binary -j .bootpg -j .resetvec
 u-boot-br.bin: u-boot FORCE
 	$(call if_changed,objcopy)
 endif
-endif
 
 quiet_cmd_ldr = LD      $@
 cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
@@ -1706,12 +1669,8 @@ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
 ifeq ($(ARCH),arm)
 UBOOT_BINLOAD := u-boot.img
 else
-ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
-UBOOT_BINLOAD := u-boot-with-dtb.bin
-else
 UBOOT_BINLOAD := u-boot.bin
 endif
-endif
 
 OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
 			  --gap-fill=0xff
@@ -2232,7 +2191,9 @@ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
 	       lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
 	       idbloader.img flash.bin flash.log defconfig keep-syms-lto.c \
 	       mkimage-out.spl.mkimage mkimage.spl.mkimage imx-boot.map \
-	       itb.fit.fit itb.fit.itb itb.map spl.map
+	       itb.fit.fit itb.fit.itb itb.map spl.map mkimage-out.rom.mkimage \
+	       mkimage.rom.mkimage rom.map simple-bin.map simple-bin-spi.map \
+	       idbloader-spi.img
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config include/generated spl tpl \

arch/arm/Kconfig

@@ -1986,7 +1986,7 @@ config ARCH_STM32MP
 config ARCH_ROCKCHIP
 	bool "Support Rockchip SoCs"
 	select BLK
-	select BINMAN if SPL_OPTEE || (SPL && !ARM64)
+	select BINMAN if SPL_OPTEE || SPL
 	select DM
 	select DM_GPIO
 	select DM_I2C

arch/arm/cpu/armv8/fsl-layerscape/spl.c

@@ -67,11 +67,24 @@ void spl_board_init(void)
 #endif
 }
 
+void tzpc_init(void)
+{
+	/*
+	 * Mark the whole OCRAM as non-secure, otherwise DMA devices cannot
+	 * access it. This is for example necessary for MMC boot.
+	 */
+#ifdef TZPCR0SIZE_BASE
+	out_le32(TZPCR0SIZE_BASE, 0);
+#endif
+}
+
 void board_init_f(ulong dummy)
 {
 	int ret;
 
 	icache_enable();
+	tzpc_init();
+
 	/* Clear global data */
 	memset((void *)gd, 0, sizeof(gd_t));
 	if (IS_ENABLED(CONFIG_DEBUG_UART))

arch/arm/cpu/armv8/sec_firmware.c

@@ -36,9 +36,6 @@ phys_addr_t sec_firmware_addr;
 #ifndef SEC_FIRMWARE_FIT_IMAGE
 #define SEC_FIRMWARE_FIT_IMAGE		"firmware"
 #endif
-#ifndef SEC_FIRMWARE_FIT_CNF_NAME
-#define SEC_FIRMWARE_FIT_CNF_NAME	"config-1"
-#endif
 #ifndef SEC_FIRMWARE_TARGET_EL
 #define SEC_FIRMWARE_TARGET_EL		2
 #endif
@@ -46,46 +43,8 @@ phys_addr_t sec_firmware_addr;
 static int sec_firmware_get_data(const void *sec_firmware_img,
 				const void **data, size_t *size)
 {
-	int conf_node_off, fw_node_off;
+	return fit_get_data_conf_prop(sec_firmware_img, SEC_FIRMWARE_FIT_IMAGE,
-	char *conf_node_name = NULL;
+				      data, size);
-	char *desc;
-	int ret;
-
-	conf_node_name = SEC_FIRMWARE_FIT_CNF_NAME;
-
-	conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
-	if (conf_node_off < 0) {
-		printf("SEC Firmware: %s: no such config\n", conf_node_name);
-		return -ENOENT;
-	}
-
-	fw_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
-			SEC_FIRMWARE_FIT_IMAGE);
-	if (fw_node_off < 0) {
-		printf("SEC Firmware: No '%s' in config\n",
-		       SEC_FIRMWARE_FIT_IMAGE);
-		return -ENOLINK;
-	}
-
-	/* Verify secure firmware image */
-	if (!(fit_image_verify(sec_firmware_img, fw_node_off))) {
-		printf("SEC Firmware: Bad firmware image (bad CRC)\n");
-		return -EINVAL;
-	}
-
-	if (fit_image_get_data(sec_firmware_img, fw_node_off, data, size)) {
-		printf("SEC Firmware: Can't get %s subimage data/size",
-		       SEC_FIRMWARE_FIT_IMAGE);
-		return -ENOENT;
-	}
-
-	ret = fit_get_desc(sec_firmware_img, fw_node_off, &desc);
-	if (ret)
-		printf("SEC Firmware: Can't get description\n");
-	else
-		printf("%s\n", desc);
-
-	return ret;
 }
 
 /*
@@ -124,18 +83,15 @@ static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
 {
 	phys_addr_t sec_firmware_loadable_addr = 0;
 	int conf_node_off, ld_node_off, images;
-	char *conf_node_name = NULL;
 	const void *data;
 	size_t size;
 	ulong load;
 	const char *name, *str, *type;
 	int len;
 
-	conf_node_name = SEC_FIRMWARE_FIT_CNF_NAME;
+	conf_node_off = fit_conf_get_node(sec_firmware_img, NULL);
-
-	conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
 	if (conf_node_off < 0) {
-		printf("SEC Firmware: %s: no such config\n", conf_node_name);
+		puts("SEC Firmware: no config\n");
 		return -ENOENT;
 	}
 

arch/arm/dts/Makefile

@@ -893,6 +893,7 @@ dtb-$(CONFIG_MX6ULL) += \
 	imx6ull-phytec-segin-ff-rdk-emmc.dtb \
 	imx6ull-dart-6ul.dtb \
 	imx6ull-somlabs-visionsom.dtb \
+	imx6ulz-bsh-smm-m2.dtb \
 	imx6ulz-14x14-evk.dtb
 
 dtb-$(CONFIG_ARCH_MX6) += \
@@ -972,13 +973,15 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mp-venice-gw74xx.dtb \
 	imx8mp-verdin-wifi-dev.dtb \
 	imx8mq-pico-pi.dtb \
-	imx8mq-kontron-pitx-imx8m.dtb
+	imx8mq-kontron-pitx-imx8m.dtb \
+	imx8mq-librem5-r4.dtb
 
 dtb-$(CONFIG_ARCH_IMX9) += \
 	imx93-11x11-evk.dtb
 
 dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
-	imxrt1020-evk.dtb
+	imxrt1020-evk.dtb \
+	imxrt1170-evk.dtb \
 
 dtb-$(CONFIG_RCAR_GEN2) += \
 	r8a7790-lager-u-boot.dtb \

arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi

@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BSH Hausgeraete GmbH
+ *
+ * Author: Michael Trimarchi <michael@amarulasolutions.com>
+ */
+
+&{/soc} {
+	u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+	u-boot,dm-pre-reloc;
+};
+
+&iomuxc {
+	u-boot,dm-pre-reloc;
+};
+
+&iomuxc_snvs {
+	u-boot,dm-pre-reloc;
+};
+
+&uart4 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart4 {
+	u-boot,dm-pre-reloc;
+};
+
+&gpmi {
+	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+};

arch/arm/dts/imx6ulz-bsh-smm-m2.dts

@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 BSH Hausgeraete GmbH
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ulz.dtsi"
+
+/ {
+	model = "BSH SMM M2";
+	compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz";
+
+	chosen {
+		stdout-path = &uart4;
+	};
+
+	usdhc2_pwrseq: usdhc2-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	nand-on-flash-bbt;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm4330-bt";
+		max-speed = <3000000>;
+		shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+		device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&usbotg1 {
+	dr_mode = "peripheral";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbphy1 {
+	fsl,tx-d-cal = <106>;
+};
+
+&usdhc2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wlan>;
+	bus-width = <4>;
+	no-1-8-v;
+	non-removable;
+	cap-power-off-card;
+	keep-power-in-suspend;
+	cap-sdio-irq;
+	mmc-pwrseq = <&usdhc2_pwrseq>;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+		interrupt-parent = <&gpio1>;
+		interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wake";
+	};
+};
+
+&wdog1 {
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_gpmi_nand: gpmi-nand {
+		fsl,pins = <
+			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0xb0b1
+			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0xb0b1
+			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0xb0b1
+			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0xb000
+			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0xb0b1
+			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0xb0b1
+			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0xb0b1
+			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0xb0b1
+			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0xb0b1
+			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0xb0b1
+			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0xb0b1
+			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0xb0b1
+			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0xb0b1
+			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0xb0b1
+			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0xb0b1
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b1
+			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b099
+			MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS	0x1b0b1
+			MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS	0x1b099
+			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0x79		/* BT_REG_ON */
+			MX6UL_PAD_SD1_CLK__GPIO2_IO17		0x100b1		/* BT_DEV_WAKE out */
+			MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13	0x1b0b0		/* BT_HOST_WAKE in */
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX	0x1b0b1
+			MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX	0x1b0b1
+		>;
+	};
+
+	pinctrl_wlan: wlangrp {
+		fsl,pins = <
+			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
+			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x10059
+			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x17059
+			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x17059
+			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x17059
+			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
+			MX6UL_PAD_SD1_DATA3__GPIO2_IO21		0x79		/* WL_REG_ON */
+			MX6UL_PAD_UART2_CTS_B__GPIO1_IO22	0x100b1		/* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */
+			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x1b0b1		/* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */
+			MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT	0x4001b031	/* OSC 32Khz wifi clk in */
+		>;
+	};
+};

arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi

@@ -106,6 +106,10 @@
 	u-boot,off-on-delay-us = <20000>;
 };
 
+&spba1 {
+	u-boot,dm-spl;
+};
+
 &uart2 {
 	u-boot,dm-spl;
 };

arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi

@@ -3,139 +3,4 @@
  * Copyright (C) 2022 Marek Vasut <marex@denx.de>
  */
 
-#include "imx8mp-u-boot.dtsi"
+#include "imx8mp-dhcom-u-boot.dtsi"
-
-/ {
-	aliases {
-		eeprom0 = &eeprom0;
-		eeprom1 = &eeprom1;
-		mmc0 = &usdhc2;	/* MicroSD */
-		mmc1 = &usdhc3;	/* eMMC */
-		mmc2 = &usdhc1;	/* SDIO */
-	};
-
-	config {
-		dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>;
-	};
-
-	wdt-reboot {
-		compatible = "wdt-reboot";
-		wdt = <&wdog1>;
-		u-boot,dm-spl;
-	};
-};
-
-&buck4 {
-	u-boot,dm-spl;
-};
-
-&buck5 {
-	u-boot,dm-spl;
-};
-
-&eqos {
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	/delete-property/ assigned-clock-rates;
-};
-
-&gpio1 {
-	u-boot,dm-spl;
-};
-
-&gpio2 {
-	u-boot,dm-spl;
-};
-
-&gpio3 {
-	u-boot,dm-spl;
-};
-
-&gpio4 {
-	u-boot,dm-spl;
-};
-
-&gpio5 {
-	u-boot,dm-spl;
-};
-
-&i2c3 {
-	u-boot,dm-spl;
-};
-
-&pinctrl_i2c3 {
-	u-boot,dm-spl;
-};
-
-&pinctrl_i2c3_gpio {
-	u-boot,dm-spl;
-};
-
-&pinctrl_pmic {
-	u-boot,dm-spl;
-};
-
-&pinctrl_uart1 {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2 {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2_100mhz {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2_200mhz {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2_vmmc {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3_100mhz {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3_100mhz {
-	u-boot,dm-spl;
-};
-
-&pmic {
-	u-boot,dm-spl;
-
-	regulators {
-		u-boot,dm-spl;
-	};
-};
-
-&reg_usdhc2_vmmc {
-	u-boot,dm-spl;
-};
-
-&uart1 {
-	u-boot,dm-spl;
-};
-
-/* SDIO WiFi */
-&usdhc1 {
-	status = "disabled";
-};
-
-&usdhc2 {
-	u-boot,dm-spl;
-};
-
-&usdhc3 {
-	u-boot,dm-spl;
-};
-
-&wdog1 {
-	u-boot,dm-spl;
-};

arch/arm/dts/imx8mp-dhcom-pdk2.dts

@@ -1,18 +1,23 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ *
+ * DHCOM iMX8MP variant:
+ * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
+ * DHCOM PCB number: 660-100 or newer
+ * PDK2 PCB number: 516-400 or newer
  */
 
 /dts-v1/;
 
 #include <dt-bindings/leds/common.h>
-#include <dt-bindings/net/qca-ar803x.h>
 #include <dt-bindings/phy/phy-imx8-pcie.h>
 #include "imx8mp-dhcom-som.dtsi"
 
 / {
 	model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)";
-	compatible = "dh,imx8mp-dhcom-pdk2", "fsl,imx8mp";
+	compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som",
+	             "fsl,imx8mp";
 
 	chosen {
 		stdout-path = &uart1;

arch/arm/dts/imx8mp-dhcom-som.dtsi

@@ -70,7 +70,7 @@
 &ecspi1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi1>;
-	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
 	status = "disabled";
 };
 
@@ -415,8 +415,8 @@
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c5>;
 	pinctrl-1 = <&pinctrl_i2c5_gpio>;
-	scl-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-	sda-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 };
 
@@ -660,10 +660,10 @@
 
 	pinctrl_ecspi1: dhcom-ecspi1-grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x44
+			MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK		0x44
-			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x44
+			MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI		0x44
-			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x44
+			MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO		0x44
-			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40
+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x40
 		>;
 	};
 

arch/arm/dts/imx8mp-dhcom-u-boot.dtsi

@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+	aliases {
+		eeprom0 = &eeprom0;
+		eeprom1 = &eeprom1;
+		mmc0 = &usdhc2;	/* MicroSD */
+		mmc1 = &usdhc3;	/* eMMC */
+		mmc2 = &usdhc1;	/* SDIO */
+	};
+
+	config {
+		dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>;
+	};
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		u-boot,dm-spl;
+	};
+};
+
+&buck4 {
+	u-boot,dm-spl;
+};
+
+&buck5 {
+	u-boot,dm-spl;
+};
+
+&eqos {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&i2c3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_i2c3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_i2c3_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+	u-boot,dm-spl;
+};
+
+&pinctrl_uart1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_200mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_100mhz {
+	u-boot,dm-spl;
+};
+
+&pmic {
+	u-boot,dm-spl;
+
+	regulators {
+		u-boot,dm-spl;
+	};
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&uart1 {
+	u-boot,dm-spl;
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+	status = "disabled";
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+};
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
+
+&wdog1 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi

@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+&pinctrl_uart1 {
+	u-boot,dm-spl;
+};
+
+&uart1 { /* console */
+	u-boot,dm-spl;
+};
+
+&binman {
+	/delete-node/ signed-hdmi;
+
+	signed-hdmi {
+		filename = "signed_hdmi.bin";
+
+		signed-dp-imx8m {
+			filename = "signed_dp_imx8m.bin";
+			type = "blob-ext";
+		};
+	};
+};

arch/arm/dts/imx8mq-librem5-r4.dts

@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Purism SPC <kernel@puri.sm>
+
+/dts-v1/;
+
+#include "imx8mq-librem5.dtsi"
+
+/ {
+	model = "Purism Librem 5r4";
+	compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq";
+};
+
+&accel_gyro {
+	mount-matrix =  "1",  "0",  "0",
+			"0",  "1",  "0",
+			"0",  "0", "-1";
+};
+
+&bat {
+	maxim,rsns-microohm = <1667>;
+};
+
+&bq25895 {
+	ti,battery-regulation-voltage = <4200000>; /* uV */
+	ti,charge-current = <1500000>; /* uA */
+	ti,termination-current = <144000>;  /* uA */
+};
+
+&led_backlight {
+	led-max-microamp = <25000>;
+};
+
+&proximity {
+	proximity-near-level = <10>;
+};

arch/arm/dts/imxrt1170-evk-u-boot.dtsi

@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
+ * Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/ {
+	chosen {
+		u-boot,dm-spl;
+	};
+
+	clocks {
+		u-boot,dm-spl;
+	};
+
+	soc {
+		u-boot,dm-spl;
+	};
+};
+
+&osc {
+	u-boot,dm-spl;
+};
+
+&rcosc16M {
+	u-boot,dm-spl;
+};
+
+&osc32k {
+	u-boot,dm-spl;
+};
+
+&clks {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&gpt1 {
+	u-boot,dm-spl;
+};
+
+&lpuart1 { /* console */
+	u-boot,dm-spl;
+};
+
+&semc {
+	u-boot,dm-spl;
+
+	bank1: bank@0 {
+		u-boot,dm-spl;
+	};
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+
+	imxrt1170-evk {
+		u-boot,dm-spl;
+		pinctrl_lpuart1: lpuart1grp {
+			u-boot,dm-spl;
+		};
+
+		pinctrl_usdhc0: usdhc0grp {
+			u-boot,dm-spl;
+		};
+		pinctrl_semc: semcgrp {
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imxrt1170-evk.dts

@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
+ * Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/dts-v1/;
+#include "imxrt1170.dtsi"
+#include "imxrt1170-evk-u-boot.dtsi"
+#include "imxrt1170-pinfunc.h"
+
+/ {
+	model = "NXP imxrt1170-evk board";
+	compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		tick-timer = &gpt1;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x20240000 0xf0000 0x80000000 0x4000000>;
+
+		ocram: ocram@20240000 {
+			device_type = "memory";
+			reg = <0x20240000 0xf0000>;
+		};
+
+		sdram: sdram@80000000 {
+			device_type = "memory";
+			reg = <0x80000000 0x4000000>;
+		};
+	};
+};
+
+&lpuart1 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+	status = "okay";
+};
+
+&semc {
+	/*
+	 * Memory configuration from sdram datasheet IS42S16160J-6BLI
+	 */
+	fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
+				0
+				0
+				0
+				0
+				0>;
+	fsl,sdram-control = /bits/ 8 <MEM_WIDTH_32BITS
+					BL_8
+					COL_9BITS
+					CL_3>;
+	fsl,sdram-timing = /bits/ 8 <0x2
+				     0x2
+				     0xd
+				     0x0
+				     0x8
+				     0x7
+
+				     0x0d
+				     0x0b
+				     0x00
+				     0x00
+
+				     0x00
+				     0x0A
+				     0x08
+				     0x09>;
+
+	bank1: bank@0 {
+		fsl,base-address = <0x80000000>;
+		fsl,memory-size = <MEM_SIZE_64M>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+
+	imxrt1170-evk {
+		pinctrl_lpuart1: lpuart1grp {
+			fsl,pins = <
+				IOMUXC_GPIO_AD_24_LPUART1_TXD 0xf1
+				IOMUXC_GPIO_AD_25_LPUART1_RXD 0xf1
+			>;
+		};
+
+		pinctrl_usdhc0: usdhc0grp {
+			fsl,pins = <
+				IOMUXC_GPIO_AD_32_USDHC1_CD_B
+					0x1B000
+				IOMUXC_GPIO_AD_34_USDHC1_VSELECT
+					0xB069
+				IOMUXC_GPIO_SD_B1_00_USDHC1_CMD
+					0x17061
+				IOMUXC_GPIO_SD_B1_01_USDHC1_CLK
+					0x17061
+				IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3
+					0x17061
+				IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2
+					0x17061
+				IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1
+					0x17061
+				IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0
+					0x17061
+			>;
+		};
+		pinctrl_semc: semcgrp {
+			fsl,pins = <
+				IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00
+					8	/* SEMC_D0 */
+				IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01
+					8	/* SEMC_D1 */
+				IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02
+					8	/* SEMC_D2 */
+				IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03
+					8	/* SEMC_D3 */
+				IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04
+					8	/* SEMC_D4 */
+				IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05
+					8	/* SEMC_D5 */
+				IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06
+					8	/* SEMC_D6 */
+				IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07
+					8	/* SEMC_D7 */
+				IOMUXC_GPIO_EMC_B1_08_SEMC_DM00
+					8	/* SEMC_DM0 */
+				IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00
+					8	/* SEMC_A0 */
+				IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01
+					8	/* SEMC_A1 */
+				IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02
+					8	/* SEMC_A2 */
+				IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03
+					8	/* SEMC_A3 */
+				IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04
+					8	/* SEMC_A4 */
+				IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05
+					8	/* SEMC_A5 */
+				IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06
+					8	/* SEMC_A6 */
+				IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07
+					8	/* SEMC_A7 */
+				IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08
+					8	/* SEMC_A8 */
+				IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09
+					8	/* SEMC_A9 */
+				IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11
+					8	/* SEMC_A11 */
+				IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12
+					8	/* SEMC_A12 */
+				IOMUXC_GPIO_EMC_B1_21_SEMC_BA0
+					8	/* SEMC_BA0 */
+				IOMUXC_GPIO_EMC_B1_22_SEMC_BA1
+					8	/* SEMC_BA1 */
+				IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10
+					8	/* SEMC_A10 */
+				IOMUXC_GPIO_EMC_B1_24_SEMC_CAS
+					8	/* SEMC_CAS */
+				IOMUXC_GPIO_EMC_B1_25_SEMC_RAS
+					8	/* SEMC_RAS */
+				IOMUXC_GPIO_EMC_B1_26_SEMC_CLK
+					8	/* SEMC_CLK */
+				IOMUXC_GPIO_EMC_B1_27_SEMC_CKE
+					8	/* SEMC_CKE */
+				IOMUXC_GPIO_EMC_B1_28_SEMC_WE
+					8	/* SEMC_WE */
+				IOMUXC_GPIO_EMC_B1_29_SEMC_CS0
+					8	/* SEMC_CS0 */
+				IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08
+					8	/* SEMC_D8 */
+				IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09
+					8	/* SEMC_D9 */
+				IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10
+					8	/* SEMC_D10 */
+				IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11
+					8	/* SEMC_D11 */
+				IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12
+					8	/* SEMC_D12 */
+				IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13
+					8	/* SEMC_D13 */
+				IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14
+					8	/* SEMC_D14 */
+				IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15
+					8	/* SEMC_D15 */
+				IOMUXC_GPIO_EMC_B1_08_SEMC_DM00
+					8	/* SEMC_DM00 */
+				IOMUXC_GPIO_EMC_B1_38_SEMC_DM01
+					8	/* SEMC_DM01 */
+				IOMUXC_GPIO_EMC_B2_08_SEMC_DM02
+					4	/* SEMC_DM02 */
+				IOMUXC_GPIO_EMC_B2_17_SEMC_DM03
+					8	/* SEMC_DM03 */
+				IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16
+					8	/* SEMC_D16 */
+				IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17
+					8	/* SEMC_D17 */
+				IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18
+					8	/* SEMC_D18 */
+				IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19
+					8	/* SEMC_D19 */
+				IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20
+					8	/* SEMC_D20 */
+				IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21
+					8	/* SEMC_D21 */
+				IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22
+					8	/* SEMC_D22 */
+				IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23
+					8	/* SEMC_D23 */
+				IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24
+					8	/* SEMC_D24 */
+				IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25
+					8	/* SEMC_D25 */
+				IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26
+					4	/* SEMC_D26 */
+				IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27
+					8	/* SEMC_D27 */
+				IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28
+					8	/* SEMC_D28 */
+				IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29
+					8	/* SEMC_D29 */
+				IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30
+					8	/* SEMC_D30 */
+				IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31
+					8	/* SEMC_D31 */
+				IOMUXC_GPIO_EMC_B1_39_SEMC_DQS
+					(IMX_PAD_SION | 8)	/* SEMC_DQS */
+			>;
+		};
+	};
+};
+
+&gpt1 {
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc0>;
+	pinctrl-1 = <&pinctrl_usdhc0>;
+	pinctrl-2 = <&pinctrl_usdhc0>;
+	pinctrl-3 = <&pinctrl_usdhc0>;
+	status = "okay";
+	broken-cd;
+};

arch/arm/dts/imxrt1170.dtsi

@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
+ * Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt1170-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/memory/imxrt-sdram.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		gpio5 = &gpio6;
+		gpio6 = &gpio7;
+		gpio7 = &gpio8;
+		gpio8 = &gpio9;
+		gpio9 = &gpio10;
+		gpio10 = &gpio11;
+		gpio11 = &gpio12;
+		gpio12 = &gpio13;
+		mmc0 = &usdhc1;
+		serial0 = &lpuart1;
+	};
+
+	clocks {
+		osc: osc {
+			compatible = "fsl,imx-osc", "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <24000000>;
+		};
+
+		rcosc16M: rcosc16M {
+			compatible = "fsl,imx-osc", "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <16000000>;
+		};
+
+		osc32k: osc32k {
+			compatible = "fsl,imx-osc", "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+
+	};
+
+	soc {
+		semc: semc@400d4000 {
+			compatible = "fsl,imxrt-semc";
+			reg = <0x400d4000 0x4000>;
+			interrupts = <132>;
+			clocks = <&clks IMXRT1170_CLK_SEMC>;
+			pinctrl-0 = <&pinctrl_semc>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+
+		lpuart1: serial@4007c000 {
+			compatible = "fsl,imxrt-lpuart";
+			reg = <0x4007c000 0x4000>;
+			interrupts = <20>;
+			clocks = <&clks IMXRT1170_CLK_LPUART1>;
+			clock-names = "per";
+			status = "disabled";
+		};
+
+		iomuxc: iomuxc@400e8000 {
+			compatible = "fsl,imxrt-iomuxc";
+			reg = <0x400e8000 0x4000>;
+			fsl,mux_mask = <0x7>;
+		};
+
+		anatop: anatop@40c84000 {
+			compatible = "fsl,imxrt-anatop";
+			reg = <0x40c84000 0x4000>;
+		};
+
+		clks: ccm@40cc0000 {
+			compatible = "fsl,imxrt1170-ccm";
+			reg = <0x40cc0000 0x4000>;
+			#clock-cells = <1>;
+		};
+
+		usdhc1: usdhc@40418000 {
+			compatible = "fsl,imxrt-usdhc";
+			reg = <0x40418000 0x10000>;
+			interrupts = <133>;
+			clocks = <&clks IMXRT1170_CLK_USDHC1>;
+			clock-names = "per";
+			bus-width = <4>;
+			fsl,tuning-start-tap = <20>;
+			fsl,tuning-step= <2>;
+			status = "disabled";
+		};
+
+		gpio1: gpio@4012c000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x4012c000 0x4000>;
+			interrupts = <100>,
+				     <101>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio@40130000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x40130000 0x4000>;
+			interrupts = <102>,
+				<103>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio3: gpio@40134000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x40134000 0x4000>;
+			interrupts = <104>,
+				<105>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio4: gpio@40138000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x40138000 0x4000>;
+			interrupts = <106>,
+					<107>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio5: gpio@4013c000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x4013c000 0x4000>;
+			interrupts = <108>,
+				<109>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio6: gpio@40140000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x40140000 0x4000>;
+			interrupts = <61>,
+				<62>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio7: gpio@40c5c000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x40c5c000 0x4000>;
+			interrupts = <99>,
+				<99>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio8: gpio@40c60000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x40c60000 0x4000>;
+			interrupts = <99>,
+				<99>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio9: gpio@40c64000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x40c64000 0x4000>;
+			interrupts = <99>,
+				<99>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio10: gpio@40c68000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x40c68000 0x4000>;
+			interrupts = <99>,
+				<99>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio11: gpio@40c6c000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x40c6c000 0x4000>;
+			interrupts = <99>,
+				<99>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio12: gpio@40c70000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x40c70000 0x4000>;
+			interrupts = <61>,
+				<62>; // only cm4
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio13: gpio@40ca0000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x40ca0000 0x4000>;
+			interrupts = <93>,
+				<93>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpt1: gpt1@400ec000 {
+			compatible = "fsl,imxrt-gpt";
+			reg = <0x400ec000 0x4000>;
+			interrupts = <119>;
+			clocks = <&clks IMXRT1170_CLK_GPT1>;
+			status = "disabled";
+		};
+	};
+};

arch/arm/dts/px30-u-boot.dtsi

@@ -3,6 +3,8 @@
  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  */
 
+#include "rockchip-u-boot.dtsi"
+
 / {
 	aliases {
 		mmc0 = &emmc;

arch/arm/dts/r7s72100-gr-peach-u-boot.dts

@@ -46,8 +46,8 @@
 	};
 
 
-	rpc: rpc@ee200000 {
+	rpc: spi@ee200000 {
-		compatible = "renesas,rpc-r7s72100", "renesas,rpc";
+		compatible = "renesas,r7s72100-rpc-if";
 		reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>;
 		bank-width = <2>;
 		num-cs = <1>;

arch/arm/dts/r8a774c0-u-boot.dtsi

@@ -10,8 +10,8 @@
 
 / {
 	soc {
-		rpc: rpc@ee200000 {
+		rpc: spi@ee200000 {
-			compatible = "renesas,rcar-gen3-rpc", "renesas,rpc-r8a774c0";
+			compatible = "renesas,r8a774c0-rpc-if", "renesas,rcar-gen3-rpc-if";
 			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
 			clocks = <&cpg CPG_MOD 917>;
 			bank-width = <2>;

arch/arm/dts/r8a77950-u-boot.dtsi

@@ -13,8 +13,8 @@
 
 / {
 	soc {
-		rpc: rpc@ee200000 {
+		rpc: spi@ee200000 {
-			compatible = "renesas,rpc-r8a7795", "renesas,rpc";
+			compatible = "renesas,r8a7795-rpc-if", "renesas,rcar-gen3-rpc-if";
 			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
 			clocks = <&cpg CPG_MOD 917>;
 			bank-width = <2>;

arch/arm/dts/r8a77960-u-boot.dtsi

@@ -13,8 +13,8 @@
 
 / {
 	soc {
-		rpc: rpc@ee200000 {
+		rpc: spi@ee200000 {
-			compatible = "renesas,rpc-r8a7796", "renesas,rpc";
+			compatible = "renesas,r8a7796-rpc-if", "renesas,rcar-gen3-rpc-if";
 			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
 			clocks = <&cpg CPG_MOD 917>;
 			bank-width = <2>;

arch/arm/dts/r8a77965-u-boot.dtsi

@@ -13,8 +13,8 @@
 
 / {
 	soc {
-		rpc: rpc@ee200000 {
+		rpc: spi@ee200000 {
-			compatible = "renesas,rpc-r8a77965", "renesas,rpc";
+			compatible = "renesas,r8a77965-rpc-if", "renesas,rcar-gen3-rpc-if";
 			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
 			clocks = <&cpg CPG_MOD 917>;
 			bank-width = <2>;

arch/arm/dts/r8a77970-u-boot.dtsi

@@ -13,8 +13,8 @@
 
 / {
 	soc {
-		rpc: rpc@ee200000 {
+		rpc: spi@ee200000 {
-			compatible = "renesas,rpc-r8a77970", "renesas,rpc";
+			compatible = "renesas,r8a77970-rpc-if", "renesas,rcar-gen3-rpc-if";
 			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
 			clocks = <&cpg CPG_MOD 917>;
 			bank-width = <2>;

arch/arm/dts/r8a77980-u-boot.dtsi

@@ -13,8 +13,8 @@
 
 / {
 	soc {
-		rpc: rpc@ee200000 {
+		rpc: spi@ee200000 {
-			compatible = "renesas,rpc-r8a77980", "renesas,rpc";
+			compatible = "renesas,r8a77980-rpc-if", "renesas,rcar-gen3-rpc-if";
 			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
 			clocks = <&cpg CPG_MOD 917>;
 			bank-width = <2>;

arch/arm/dts/r8a77990-u-boot.dtsi

@@ -9,8 +9,8 @@
 
 / {
 	soc {
-		rpc: rpc@ee200000 {
+		rpc: spi@ee200000 {
-			compatible = "renesas,rpc-r8a77990", "renesas,rpc";
+			compatible = "renesas,r8a77990-rpc-if", "renesas,rcar-gen3-rpc-if";
 			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
 			clocks = <&cpg CPG_MOD 917>;
 			bank-width = <2>;

arch/arm/dts/r8a77995-u-boot.dtsi

@@ -9,8 +9,8 @@
 
 / {
 	soc {
-		rpc: rpc@ee200000 {
+		rpc: spi@ee200000 {
-			compatible = "renesas,rpc-r8a77995", "renesas,rpc";
+			compatible = "renesas,r8a77995-rpc-if", "renesas,rcar-gen3-rpc-if";
 			reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
 			clocks = <&cpg CPG_MOD 917>;
 			bank-width = <2>;

arch/arm/dts/r8a779a0-u-boot.dtsi

@@ -10,7 +10,7 @@
 / {
 	soc {
 		rpc: spi@ee200000 {
-			compatible = "renesas,rpc-r8a779a0", "renesas,rcar-gen3-rpc";
+			compatible = "renesas,r8a779a0-rpc-if", "renesas,rcar-gen3-rpc-if";
 			reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
 			clocks = <&cpg CPG_MOD 629>;
 			bank-width = <2>;

arch/arm/dts/rk3288-u-boot.dtsi

@@ -56,7 +56,7 @@
 	};
 };
 
-#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
 &binman {
 	rom {
 		filename = "u-boot.rom";

arch/arm/dts/rk3288.dtsi

@@ -109,48 +109,48 @@
 		ports = <&vopl_out>, <&vopb_out>;
 	};
 
-	sdmmc: dwmmc@ff0c0000 {
+	sdmmc: mmc@ff0c0000 {
 		compatible = "rockchip,rk3288-dw-mshc";
 		max-frequency = <150000000>;
 		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 		fifo-depth = <0x100>;
 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 		reg = <0xff0c0000 0x4000>;
 		status = "disabled";
 	};
 
-	sdio0: dwmmc@ff0d0000 {
+	sdio0: mmc@ff0d0000 {
 		compatible = "rockchip,rk3288-dw-mshc";
 		max-frequency = <150000000>;
 		clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 			 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 		fifo-depth = <0x100>;
 		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 		reg = <0xff0d0000 0x4000>;
 		status = "disabled";
 	};
 
-	sdio1: dwmmc@ff0e0000 {
+	sdio1: mmc@ff0e0000 {
 		compatible = "rockchip,rk3288-dw-mshc";
 		max-frequency = <150000000>;
 		clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 			 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 		fifo-depth = <0x100>;
 		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 		reg = <0xff0e0000 0x4000>;
 		status = "disabled";
 	};
 
-	emmc: dwmmc@ff0f0000 {
+	emmc: mmc@ff0f0000 {
 		compatible = "rockchip,rk3288-dw-mshc";
 		max-frequency = <150000000>;
 		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 		fifo-depth = <0x100>;
 		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 		reg = <0xff0f0000 0x4000>;

arch/arm/dts/rk3308-u-boot.dtsi

@@ -3,6 +3,8 @@
  *(C) Copyright 2019 Rockchip Electronics Co., Ltd
  */
 
+#include "rockchip-u-boot.dtsi"
+
 / {
 	aliases {
 		mmc0 = &emmc;

arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi

@@ -3,6 +3,8 @@
  * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
  */
 
+#include "rockchip-u-boot.dtsi"
+
 / {
 	chosen {
 		u-boot,spl-boot-order = &sdmmc;

arch/arm/dts/rk3328-u-boot.dtsi

@@ -3,6 +3,8 @@
  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  */
 
+#include "rockchip-u-boot.dtsi"
+
 / {
 	aliases {
 		mmc0 = &emmc;

arch/arm/dts/rk3368-u-boot.dtsi

@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/memory/rk3368-dmc.h>
+#include "rockchip-u-boot.dtsi"
 
 / {
 	dmc: dmc@ff610000 {

arch/arm/dts/rk3399-u-boot.dtsi

@@ -60,7 +60,7 @@
 
 };
 
-#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
 &binman {
 	rom {
 		filename = "u-boot.rom";

arch/arm/dts/rk3568-u-boot.dtsi

@@ -3,6 +3,8 @@
  * (C) Copyright 2021 Rockchip Electronics Co., Ltd
  */
 
+#include "rockchip-u-boot.dtsi"
+
 / {
 	aliases {
 		mmc0 = &sdhci;

arch/arm/dts/rockchip-u-boot.dtsi

@@ -17,13 +17,57 @@
 		filename = "u-boot-rockchip.bin";
 		pad-byte = <0xff>;
 
-		blob {
+		mkimage {
 			filename = "idbloader.img";
+			args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+#ifdef CONFIG_TPL
+			multiple-data-files;
+
+			u-boot-tpl {
+			};
+#endif
+			u-boot-spl {
+			};
 		};
 
+#ifdef CONFIG_ARM64
+		blob {
+			filename = "u-boot.itb";
+#else
 		u-boot-img {
+#endif
 			offset = <CONFIG_SPL_PAD_TO>;
 		};
 	};
+
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+	simple-bin-spi {
+		filename = "u-boot-rockchip-spi.bin";
+		pad-byte = <0xff>;
+
+		mkimage {
+			filename = "idbloader-spi.img";
+			args = "-n", CONFIG_SYS_SOC, "-T", "rkspi";
+#ifdef CONFIG_TPL
+			multiple-data-files;
+
+			u-boot-tpl {
+			};
+#endif
+			u-boot-spl {
+			};
+		};
+
+#ifdef CONFIG_ARM64
+		blob {
+			filename = "u-boot.itb";
+#else
+		u-boot-img {
+#endif
+			/* Sync with u-boot,spl-payload-offset if present */
+			offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+		};
+	};
+#endif
 };
 #endif

arch/arm/dts/stm32f746-disco-u-boot.dtsi

@@ -58,7 +58,7 @@
 				vsync-len = <10>;
 				hsync-active = <0>;
 				vsync-active = <0>;
-				de-active = <0>;
+				de-active = <1>;
 				pixelclk-active = <1>;
 			};
 		};

arch/arm/dts/stm32mp151.dtsi

@@ -1663,7 +1663,6 @@
 			ranges = <0 0x50002000 0xa400>;
 			interrupt-parent = <&exti>;
 			st,syscfg = <&exti 0x60 0xff>;
-			hwlocks = <&hwspinlock 0>;
 			pins-are-numbered;
 
 			gpioa: gpio@50002000 {
@@ -1796,7 +1795,6 @@
 			pins-are-numbered;
 			interrupt-parent = <&exti>;
 			st,syscfg = <&exti 0x60 0xff>;
-			hwlocks = <&hwspinlock 0>;
 
 			gpioz: gpio@54004000 {
 				gpio-controller;

arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi

@@ -5,14 +5,6 @@
 
 #include "stm32mp15xx-dhcom-u-boot.dtsi"
 
-/ {
-	aliases {
-		/delete-property/ ethernet1;
-	};
-};
-
-/delete-node/ &ks8851;
-
 &usbotg_hs {
 	dr_mode = "peripheral";
 };

arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

@@ -9,8 +9,6 @@
 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
 
-/delete-node/ &ksz8851;
-
 / {
 	aliases {
 		i2c1 = &i2c2;
@@ -21,7 +19,6 @@
 		spi0 = &qspi;
 		usb0 = &usbotg_hs;
 		eeprom0 = &eeprom0;
-		ethernet1 = &ks8851;
 	};
 
 	config {
@@ -30,12 +27,6 @@
 		dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
 		dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
 	};
-
-	/* This is actually on FMC2, but we do not have bus driver for that */
-	ks8851: ks8851mll@64000000 {
-		compatible = "micrel,ks8851-mll";
-		reg = <0x64000000 0x20000>;
-	};
 };
 
 &ethernet0 {
@@ -74,11 +65,6 @@
 };
 
 &pinctrl {
-	/* These should bound to FMC2 bus driver, but we do not have one */
-	pinctrl-0 = <&fmc_pins_b &mco2_pins_a>;
-	pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>;
-	pinctrl-names = "default", "sleep";
-
 	mco2_pins_a: mco2-0 {
 		pins {
 			pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */

arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi

@@ -5,25 +5,16 @@
 
 #include "stm32mp15xx-dhcor-u-boot.dtsi"
 
-/delete-node/ &ksz8851;
-
 / {
 	aliases {
 		mmc0 = &sdmmc1;
 		mmc1 = &sdmmc2;
 		usb0 = &usbotg_hs;
-		ethernet1 = &ks8851;
 	};
 
 	config {
 		dh,board-coding-gpios = <&gpioh 9 0>, <&gpioh 8 0>, <&gpioh 3 0>;
 	};
-
-	/* This is actually on FMC2, but we do not have bus driver for that */
-	ks8851: ks8851mll@64000000 {
-		compatible = "micrel,ks8851-mll";
-		reg = <0x64000000 0x20000>;
-	};
 };
 
 &ethernet0 {
@@ -38,13 +29,6 @@
 	};
 };
 
-&pinctrl {
-	/* These should bound to FMC2 bus driver, but we do not have one */
-	pinctrl-0 = <&fmc_pins_b>;
-	pinctrl-1 = <&fmc_sleep_pins_b>;
-	pinctrl-names = "default", "sleep";
-};
-
 &sdmmc1 {
 	u-boot,dm-spl;
 	st,use-ckin;

arch/arm/include/asm/arch-imx/cpu.h

@@ -56,6 +56,7 @@
 
 #define MXC_CPU_IMXRT1020	0xB4 /* dummy ID */
 #define MXC_CPU_IMXRT1050	0xB6 /* dummy ID */
+#define MXC_CPU_IMXRT1170	0xBA /* dummy ID */
 
 #define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
 #define MXC_CPU_VF610		0xF6 /* dummy ID */

arch/arm/include/asm/pl310.h

@@ -7,13 +7,12 @@
 #ifndef _PL310_H_
 #define _PL310_H_
 
-#include <linux/types.h>
-
 /* Register bit fields */
 #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK	(1 << 16)
 #define L2X0_DYNAMIC_CLK_GATING_EN		(1 << 1)
 #define L2X0_STNDBY_MODE_EN			(1 << 0)
 #define L2X0_CTRL_EN				1
+#define L2X0_CTRL_OFF				0x100
 
 #define L310_SHARED_ATT_OVERRIDE_ENABLE		(1 << 22)
 #define L310_AUX_CTRL_DATA_PREFETCH_MASK	(1 << 28)
@@ -27,6 +26,10 @@
 #define L2X0_CACHE_ID_RTL_MASK          0x3f
 #define L2X0_CACHE_ID_RTL_R3P2          0x8
 
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
 struct pl310_regs {
 	u32 pl310_cache_id;
 	u32 pl310_cache_type;
@@ -87,3 +90,5 @@ void pl310_inval_range(u32 start, u32 end);
 void pl310_clean_inval_range(u32 start, u32 end);
 
 #endif
+
+#endif

arch/arm/lib/semihosting.c

@@ -32,12 +32,12 @@ static noinline long smh_trap(unsigned int sysnum, void *addr)
 {
 	register long result asm("r0");
 #if defined(CONFIG_ARM64)
-	asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
+	asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr) : "memory");
 #elif defined(CONFIG_CPU_V7M)
-	asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr));
+	asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr) : "memory");
 #else
 	/* Note - untested placeholder */
-	asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr));
+	asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr) : "memory");
 #endif
 	return result;
 }

arch/arm/mach-imx/imx8m/Kconfig

@@ -269,6 +269,14 @@ config TARGET_IMX8MP_RSB3720A1_6G
 	select IMX8MP
 	select SUPPORT_SPL
 	select IMX8M_LPDDR4
+
+config TARGET_LIBREM5
+	bool "Purism Librem5 Phone"
+	select BINMAN
+	select IMX8MQ
+	select SUPPORT_SPL
+	select IMX8M_LPDDR4
+
 endchoice
 
 source "board/advantech/imx8mp_rsb3720a1/Kconfig"
@@ -290,6 +298,7 @@ source "board/kontron/sl-mx8mm/Kconfig"
 source "board/menlo/mx8menlo/Kconfig"
 source "board/phytec/phycore_imx8mm/Kconfig"
 source "board/phytec/phycore_imx8mp/Kconfig"
+source "board/purism/librem5/Kconfig"
 source "board/ronetix/imx8mq-cm/Kconfig"
 source "board/technexion/pico-imx8mq/Kconfig"
 source "board/variscite/imx8mn_var_som/Kconfig"

arch/arm/mach-imx/imxrt/Kconfig

@@ -12,6 +12,10 @@ config IMXRT1050
 	bool
 	select IMXRT
 
+config IMXRT1170
+	bool
+	select IMXRT
+
 config SYS_SOC
 	default "imxrt"
 
@@ -27,9 +31,14 @@ config TARGET_IMXRT1050_EVK
 	bool "Support imxrt1050 EVK board"
 	select IMXRT1050
 
+config TARGET_IMXRT1170_EVK
+	bool "Support imxrt1170 EVK board"
+	select IMXRT1170
+
 endchoice
 
 source "board/freescale/imxrt1020-evk/Kconfig"
 source "board/freescale/imxrt1050-evk/Kconfig"
+source "board/freescale/imxrt1170-evk/Kconfig"
 
 endif

arch/arm/mach-imx/imxrt/soc.c

@@ -43,6 +43,8 @@ u32 get_cpu_rev(void)
 	return MXC_CPU_IMXRT1020 << 12;
 #elif defined(CONFIG_IMXRT1050)
 	return MXC_CPU_IMXRT1050 << 12;
+#elif defined(CONFIG_IMXRT1170)
+	return MXC_CPU_IMXRT1170 << 12;
 #else
 #error This IMXRT SoC is not supported
 #endif

arch/arm/mach-imx/mx6/Kconfig

@@ -466,6 +466,17 @@ config TARGET_MX6ULL_14X14_EVK
 	select DM_THERMAL
 	imply CMD_DM
 
+config TARGET_MX6ULZ_SMM_M2
+	bool "Support imx6ulz_smm_m2"
+	depends on MX6ULL
+	select DM
+	select DM_GPIO
+	select DM_I2C
+	select DM_SERIAL
+	select DM_MTD
+	select DM_THERMAL
+	select SUPPORT_SPL
+
 config TARGET_MYS_6ULX
 	bool "MYiR MYS-6ULX"
 	depends on MX6ULL
@@ -680,6 +691,7 @@ source "board/ge/b1x5v2/Kconfig"
 source "board/aristainetos/Kconfig"
 source "board/armadeus/opos6uldev/Kconfig"
 source "board/boundary/nitrogen6x/Kconfig"
+source "board/bsh/imx6ulz_smm_m2/Kconfig"
 source "board/bticino/mamoj/Kconfig"
 source "board/compulab/cm_fx6/Kconfig"
 source "board/dhelectronics/dh_imx6/Kconfig"

arch/arm/mach-imx/spl_imx_romapi.c

@@ -288,7 +288,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image,
 	}
 
 	imagesize = img_info_size(phdr);
-	printf("Find img info 0x&%p, size %d\n", phdr, imagesize);
+	printf("Find img info 0x%p, size %d\n", phdr, imagesize);
 
 	if (p - phdr < imagesize) {
 		imagesize -= p - phdr;

arch/arm/mach-kirkwood/cpu.c

@@ -52,7 +52,7 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval)
 	return (0x0000ffff & j);
 }
 
-static struct mbus_win windows[] = {
+static const struct mbus_win windows[] = {
 	/* Window 0: PCIE MEM address space */
 	{ KW_DEFADR_PCI_MEM, KW_DEFADR_PCI_MEM_SIZE,
 	  KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },

arch/arm/mach-kirkwood/include/mach/cpu.h

@@ -150,7 +150,7 @@ struct kwgpio_registers {
 unsigned int mvebu_sdram_bar(enum memory_bank bank);
 unsigned int mvebu_sdram_bs(enum memory_bank bank);
 void mvebu_sdram_size_adjust(enum memory_bank bank);
-int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_mbus_probe(const struct mbus_win windows[], int count);
 void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
 		unsigned int gpp0_oe, unsigned int gpp1_oe);
 int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,

arch/arm/mach-mvebu/cpu.c

@@ -20,7 +20,7 @@
 #define DDR_BASE_CS_OFF(n)	(0x0000 + ((n) << 3))
 #define DDR_SIZE_CS_OFF(n)	(0x0004 + ((n) << 3))
 
-static struct mbus_win windows[] = {
+static const struct mbus_win windows[] = {
 	/* SPI */
 	{ MBUS_SPI_BASE, MBUS_SPI_SIZE,
 	  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
@@ -445,19 +445,6 @@ static void setup_usb_phys(void)
  */
 int arch_cpu_init(void)
 {
-	struct pl310_regs *const pl310 =
-		(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-
-	if (IS_ENABLED(CONFIG_ARMADA_38X)) {
-		/*
-		 * To fully release / unlock this area from cache, we need
-		 * to flush all caches and disable the L2 cache.
-		 */
-		icache_disable();
-		dcache_disable();
-		clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-	}
-
 	/*
 	 * We need to call mvebu_mbus_probe() before calling
 	 * update_sdram_window_sizes() as it disables all previously
@@ -663,7 +650,7 @@ void enable_caches(void)
 	 * ethernet driver (mvpp2). So lets keep the d-cache disabled
 	 * until this is solved.
 	 */
-	if (IS_ENABLED(CONFIG_ARMADA_375)) {
+	if (!IS_ENABLED(CONFIG_ARMADA_375)) {
 		/* Enable D-cache. I-cache is already enabled in start.S */
 		dcache_enable();
 	}
@@ -671,13 +658,21 @@ void enable_caches(void)
 
 void v7_outer_cache_enable(void)
 {
-	if (IS_ENABLED(CONFIG_ARMADA_XP)) {
 	struct pl310_regs *const pl310 =
 		(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-		u32 u;
 
 	/* The L2 cache is already disabled at this point */
 
+	/*
+	 * For now L2 cache will be enabled only for Armada XP and Armada 38x.
+	 * It can be enabled also for other SoCs after testing that it works fine.
+	 */
+	if (!IS_ENABLED(CONFIG_ARMADA_XP) && !IS_ENABLED(CONFIG_ARMADA_38X))
+		return;
+
+	if (IS_ENABLED(CONFIG_ARMADA_XP)) {
+		u32 u;
+
 		/*
 		 * For Aurora cache in no outer mode, enable via the CP15
 		 * coprocessor broadcasting of cache commands to L2.
@@ -687,10 +682,10 @@ void v7_outer_cache_enable(void)
 		asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
 
 		isb();
+	}
 
 	/* Enable the L2 cache */
 	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-	}
 }
 
 void v7_outer_cache_disable(void)

arch/arm/mach-mvebu/include/mach/cpu.h

@@ -128,7 +128,7 @@ struct sar_freq_modes {
 unsigned int mvebu_sdram_bar(enum memory_bank bank);
 unsigned int mvebu_sdram_bs(enum memory_bank bank);
 void mvebu_sdram_size_adjust(enum memory_bank bank);
-int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_mbus_probe(const struct mbus_win windows[], int count);
 u32 mvebu_get_nand_clock(void);
 
 void __noreturn return_to_bootrom(void);

arch/arm/mach-mvebu/lowlevel.S

@@ -2,6 +2,8 @@
 
 #include <config.h>
 #include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/pl310.h>
 
 ENTRY(arch_very_early_init)
 #ifdef CONFIG_ARMADA_38X
@@ -10,10 +12,36 @@ ENTRY(arch_very_early_init)
 	 * register address on Armada 38x. Without this the SDRAM
 	 * located at >= 0x4000.0000 is also not accessible, as its
 	 * still locked to cache.
+	 *
+	 * So to fully release / unlock this area from cache, we need
+	 * to first flush all caches, then disable the MMU and
+	 * disable the L2 cache.
 	 */
+
+	/* Invalidate L1 I/D */
+	mov	r0, #0			@ set up for MCR
+	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
+	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
+	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
+	mcr	p15, 0, r0, c7, c10, 4	@ DSB
+	mcr	p15, 0, r0, c7, c5, 4	@ ISB
+
+	/* Disable MMU */
 	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, #1
+	bic	r0, #CR_M
 	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Disable L2 cache
+	 *
+	 * NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG
+	 *       but CONFIG_SYS_PL310_BASE is already calculated from base
+	 *       address SOC_REGS_PHY_BASE.
+	 */
+	ldr	r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
+	ldr	r0, [r1, #L2X0_CTRL_OFF]
+	bic	r0, #L2X0_CTRL_EN
+	str	r0, [r1, #L2X0_CTRL_OFF]
 #endif
 
 	/* Move internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE */

arch/arm/mach-mvebu/mbus.c

@@ -469,7 +469,7 @@ int mbus_dt_setup_win(u32 base, u32 size, u8 target, u8 attr)
 	return 0;
 }
 
-int mvebu_mbus_probe(struct mbus_win windows[], int count)
+int mvebu_mbus_probe(const struct mbus_win windows[], int count)
 {
 	int win;
 	int ret;

arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c

@@ -105,7 +105,7 @@ struct serdes_unit_data {
 	u8 serdes_unit_num;
 };
 
-static struct serdes_unit_data serdes_type_to_unit_info[] = {
+static const struct serdes_unit_data serdes_type_to_unit_info[] = {
 	{PEX_UNIT_ID, 0,},
 	{PEX_UNIT_ID, 1,},
 	{PEX_UNIT_ID, 2,},

arch/arm/mach-mvebu/system-controller.c

@@ -86,7 +86,7 @@ static const struct udevice_id mvebu_reset_of_match[] = {
 	{ },
 };
 
-static struct reset_ops mvebu_reset_ops = {
+static const struct reset_ops mvebu_reset_ops = {
 	.of_xlate = mvebu_reset_of_xlate,
 	.request = mvebu_reset_request,
 	.rfree = mvebu_reset_free,

arch/arm/mach-rockchip/Kconfig

@@ -425,12 +425,10 @@ config SPL_MMC
 
 config ROCKCHIP_SPI_IMAGE
 	bool "Build a SPI image for rockchip"
-	depends on HAS_ROM
 	help
 	  Some Rockchip SoCs support booting from SPI flash. Enable this
-	  option to produce a 4MB SPI-flash image (called u-boot.rom)
+	  option to produce a SPI-flash image containing U-Boot. The image
-	  containing U-Boot. The image is built by binman. U-Boot sits near
+	  is built by binman. U-Boot sits near the start of the image.
-	  the start of the image.
 
 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
 	default SYS_TEXT_BASE

arch/arm/mach-rockchip/rk3308/rk3308.c

@@ -8,6 +8,7 @@
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/arch/grf_rk3308.h>
+#include <asm/arch-rockchip/bootrom.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/gpio.h>
 #include <debug_uart.h>
@@ -142,6 +143,11 @@ enum {
 
 #define GPIO0_A4	4
 
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/mmc@ff490000",
+	[BROM_BOOTSOURCE_SD] = "/mmc@ff480000",
+};
+
 int rk_board_init(void)
 {
 	static struct rk3308_grf * const grf = (void *)GRF_BASE;

arch/arm/mach-rockchip/rk3399/rk3399.c

@@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GRF_BASE	0xff770000
 
 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
-	[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
+	[BROM_BOOTSOURCE_EMMC] = "/mmc@fe330000",
 	[BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000/flash@0",
 	[BROM_BOOTSOURCE_SD] = "/mmc@fe320000",
 };
@@ -180,9 +180,9 @@ const char *spl_decode_boot_device(u32 boot_device)
 		u32 boot_device;
 		const char *ofpath;
 	} spl_boot_devices_tbl[] = {
-		{ BOOT_DEVICE_MMC1, "/mmc@fe320000" },
+		{ BOOT_DEVICE_MMC2, "/mmc@fe320000" },
-		{ BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
+		{ BOOT_DEVICE_MMC1, "/mmc@fe330000" },
-		{ BOOT_DEVICE_SPI, "/spi@ff1d0000" },
+		{ BOOT_DEVICE_SPI, "/spi@ff1d0000/flash@0" },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)

arch/arm/mach-stm32mp/stm32mp15x.c

@@ -274,7 +274,6 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
 	u32 cpu_type = get_cpu_type();
 	u32 ct = cpu_type & ~(BIT(7) | BIT(0));
 	u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0));
-	u32 cp = get_cpu_package();
 
 	/* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */
 	switch (ct) {
@@ -293,17 +292,9 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
 	}
 
 	/* Package */
-	switch (cp) {
+	*pkg = get_cpu_package();
-	case STM32MP15_PKG_AA_LBGA448:
+	if (*pkg > STM32MP15_PKG_AA_LBGA448)
-	case STM32MP15_PKG_AB_LBGA354:
+		*pkg = STM32MP15_PKG_UNKNOWN;
-	case STM32MP15_PKG_AC_TFBGA361:
-	case STM32MP15_PKG_AD_TFBGA257:
-		*pkg = cp;
-		break;
-	default:
-		*pkg = 0;
-		break;
-	}
 
 	/* Revision */
 	switch (get_cpu_rev()) {

arch/powerpc/Kconfig

@@ -21,7 +21,7 @@ config MPC85xx
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_IFC_BE
-	select BINMAN if OF_SEPARATE
+	select BINMAN if MPC85XX_HAVE_RESET_VECTOR && OF_SEPARATE
 	imply CMD_HASH
 	imply CMD_IRQ
 	imply USB_EHCI_HCD if USB

arch/powerpc/cpu/mpc85xx/Kconfig

@@ -15,7 +15,7 @@ config CMD_ERRATA
 config FSL_PREPBL_ESDHC_BOOT_SECTOR
 	bool "Generate QorIQ pre-PBL eSDHC boot sector"
 	depends on MPC85xx
-	depends on SYS_EXTRA_OPTIONS = SDCARD
+	depends on SDCARD
 	help
 	  With this option final image would have prepended QorIQ pre-PBL eSDHC
 	  boot sector suitable for SD card images. This boot sector instruct

arch/powerpc/cpu/mpc85xx/cpu.c

@@ -44,7 +44,9 @@ __board_reset(void)
 {
 	/* Do nothing */
 }
+void board_reset_prepare(void) __attribute__((weak, alias("__board_reset")));
 void board_reset(void) __attribute__((weak, alias("__board_reset")));
+void board_reset_last(void) __attribute__((weak, alias("__board_reset")));
 
 int checkcpu (void)
 {
@@ -319,12 +321,18 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 #else
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
+	/* Call board-specific preparation for reset */
+	board_reset_prepare();
+
 	/* Attempt board-specific reset */
 	board_reset();
 
 	/* Next try asserting HRESET_REQ */
 	out_be32(&gur->rstcr, 0x2);
 	udelay(100);
+
+	/* Attempt last-stage board-specific reset */
+	board_reset_last();
 #endif
 
 	return 1;

arch/powerpc/cpu/mpc85xx/u-boot-spl.lds

@@ -58,10 +58,17 @@ SECTIONS
 	__ex_table : { *(__ex_table) }
 	__stop___ex_table = .;
 
-	. = ALIGN(8);
+	. = ALIGN(4);
 	__init_begin = .;
 	__init_end = .;
 	_end = .;
+
+#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
+#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS)
+	mmc_u_boot_offs = .;
+#endif
+#endif
+
 #ifdef CONFIG_SPL_SKIP_RELOCATE
 	. = ALIGN(4);
 	__bss_start = .;
@@ -94,6 +101,9 @@ SECTIONS
 	.resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : {
 		KEEP(*(.resetvec))
 	} = 0xffff
+#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS)
+	mmc_u_boot_offs = .;
+#endif
 #endif
 
 #ifndef CONFIG_SPL_SKIP_RELOCATE

arch/powerpc/dts/kmcent2-u-boot.dtsi

@@ -76,7 +76,7 @@
 	};
 
 	binman {
-		filename = "u-boot-with-dtb.bin";
+		filename = "u-boot.bin";
 		skip-at-start = <CONFIG_SYS_TEXT_BASE>;
 		sort-by-offset;
 		pad-byte = <0xff>;

arch/powerpc/dts/u-boot.dtsi

@@ -5,9 +5,11 @@
 
 #include <config.h>
 
+#if defined(CONFIG_MPC85XX_HAVE_RESET_VECTOR) && defined(CONFIG_OF_SEPARATE)
+
 / {
 	binman {
-		filename = "u-boot-with-dtb.bin";
+		filename = "u-boot.bin";
 		skip-at-start = <CONFIG_SYS_TEXT_BASE>;
 		sort-by-offset;
 		pad-byte = <0xff>;
@@ -19,17 +21,15 @@
 		};
 
 		u-boot-dtb-with-ucode {
-#ifdef CONFIG_MPC85xx
 			align = <4>;
-#endif
 		};
-#ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 		powerpc-mpc85xx-bootpg-resetvec {
 			offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
 		};
-#endif
 	};
 };
+
+#endif

arch/riscv/dts/fu740-c000-u-boot.dtsi

@@ -7,11 +7,11 @@
 
 / {
 	cpus {
-		assigned-clocks = <&prci PRCI_CLK_COREPLL>;
+		assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
 		assigned-clock-rates = <1200000000>;
 		u-boot,dm-spl;
 		cpu0: cpu@0 {
-			clocks = <&prci PRCI_CLK_COREPLL>;
+			clocks = <&prci FU740_PRCI_CLK_COREPLL>;
 			u-boot,dm-spl;
 			status = "okay";
 			cpu0_intc: interrupt-controller {
@@ -19,28 +19,28 @@
 			};
 		};
 		cpu1: cpu@1 {
-			clocks = <&prci PRCI_CLK_COREPLL>;
+			clocks = <&prci FU740_PRCI_CLK_COREPLL>;
 			u-boot,dm-spl;
 			cpu1_intc: interrupt-controller {
 				u-boot,dm-spl;
 			};
 		};
 		cpu2: cpu@2 {
-			clocks = <&prci PRCI_CLK_COREPLL>;
+			clocks = <&prci FU740_PRCI_CLK_COREPLL>;
 			u-boot,dm-spl;
 			cpu2_intc: interrupt-controller {
 				 u-boot,dm-spl;
 			};
 		};
 		cpu3: cpu@3 {
-			clocks = <&prci PRCI_CLK_COREPLL>;
+			clocks = <&prci FU740_PRCI_CLK_COREPLL>;
 			u-boot,dm-spl;
 			cpu3_intc: interrupt-controller {
 				u-boot,dm-spl;
 			};
 		};
 		cpu4: cpu@4 {
-			clocks = <&prci PRCI_CLK_COREPLL>;
+			clocks = <&prci FU740_PRCI_CLK_COREPLL>;
 			u-boot,dm-spl;
 			cpu4_intc: interrupt-controller {
 				u-boot,dm-spl;
@@ -76,7 +76,7 @@
 			reg = <0x0 0x100b0000 0x0 0x0800
 			       0x0 0x100b2000 0x0 0x2000
 			       0x0 0x100b8000 0x0 0x1000>;
-			clocks = <&prci PRCI_CLK_DDRPLL>;
+			clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
 			clock-frequency = <933333324>;
 			u-boot,dm-spl;
 		};
@@ -100,7 +100,7 @@
 };
 
 &eth0 {
-	assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
+	assigned-clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>;
 	assigned-clock-rates = <125125000>;
 };
 

arch/riscv/dts/fu740-c000.dtsi

@@ -1,10 +1,9 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020-2021 SiFive, Inc */
+/* Copyright (c) 2020 SiFive, Inc */
 
 /dts-v1/;
 
 #include <dt-bindings/clock/sifive-fu740-prci.h>
-#include <dt-bindings/reset/sifive-fu740-prci.h>
 
 / {
 	#address-cells = <2>;
@@ -139,20 +138,21 @@
 	soc {
 		#address-cells = <2>;
 		#size-cells = <2>;
-		compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
+		compatible = "simple-bus";
 		ranges;
 		plic0: interrupt-controller@c000000 {
 			#interrupt-cells = <1>;
-			compatible = "sifive,plic-1.0.0";
+			#address-cells = <0>;
+			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
 			riscv,ndev = <69>;
 			interrupt-controller;
-			interrupts-extended = <
+			interrupts-extended =
-				&cpu0_intc 0xffffffff
+				<&cpu0_intc 0xffffffff>,
-				&cpu1_intc 0xffffffff &cpu1_intc 9
+				<&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
-				&cpu2_intc 0xffffffff &cpu2_intc 9
+				<&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
-				&cpu3_intc 0xffffffff &cpu3_intc 9
+				<&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
-				&cpu4_intc 0xffffffff &cpu4_intc 9>;
+				<&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
 		};
 		prci: clock-controller@10000000 {
 			compatible = "sifive,fu740-c000-prci";
@@ -166,7 +166,7 @@
 			reg = <0x0 0x10010000 0x0 0x1000>;
 			interrupt-parent = <&plic0>;
 			interrupts = <39>;
-			clocks = <&prci PRCI_CLK_PCLK>;
+			clocks = <&prci FU740_PRCI_CLK_PCLK>;
 			status = "disabled";
 		};
 		uart1: serial@10011000 {
@@ -174,7 +174,7 @@
 			reg = <0x0 0x10011000 0x0 0x1000>;
 			interrupt-parent = <&plic0>;
 			interrupts = <40>;
-			clocks = <&prci PRCI_CLK_PCLK>;
+			clocks = <&prci FU740_PRCI_CLK_PCLK>;
 			status = "disabled";
 		};
 		i2c0: i2c@10030000 {
@@ -182,7 +182,7 @@
 			reg = <0x0 0x10030000 0x0 0x1000>;
 			interrupt-parent = <&plic0>;
 			interrupts = <52>;
-			clocks = <&prci PRCI_CLK_PCLK>;
+			clocks = <&prci FU740_PRCI_CLK_PCLK>;
 			reg-shift = <2>;
 			reg-io-width = <1>;
 			#address-cells = <1>;
@@ -194,7 +194,7 @@
 			reg = <0x0 0x10031000 0x0 0x1000>;
 			interrupt-parent = <&plic0>;
 			interrupts = <53>;
-			clocks = <&prci PRCI_CLK_PCLK>;
+			clocks = <&prci FU740_PRCI_CLK_PCLK>;
 			reg-shift = <2>;
 			reg-io-width = <1>;
 			#address-cells = <1>;
@@ -203,22 +203,22 @@
 		};
 		qspi0: spi@10040000 {
 			compatible = "sifive,fu740-c000-spi", "sifive,spi0";
-			reg = <0x0 0x10040000 0x0 0x1000
+			reg = <0x0 0x10040000 0x0 0x1000>,
-			       0x0 0x20000000 0x0 0x10000000>;
+			      <0x0 0x20000000 0x0 0x10000000>;
 			interrupt-parent = <&plic0>;
 			interrupts = <41>;
-			clocks = <&prci PRCI_CLK_PCLK>;
+			clocks = <&prci FU740_PRCI_CLK_PCLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 		};
 		qspi1: spi@10041000 {
 			compatible = "sifive,fu740-c000-spi", "sifive,spi0";
-			reg = <0x0 0x10041000 0x0 0x1000
+			reg = <0x0 0x10041000 0x0 0x1000>,
-			       0x0 0x30000000 0x0 0x10000000>;
+			      <0x0 0x30000000 0x0 0x10000000>;
 			interrupt-parent = <&plic0>;
 			interrupts = <42>;
-			clocks = <&prci PRCI_CLK_PCLK>;
+			clocks = <&prci FU740_PRCI_CLK_PCLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -228,7 +228,7 @@
 			reg = <0x0 0x10050000 0x0 0x1000>;
 			interrupt-parent = <&plic0>;
 			interrupts = <43>;
-			clocks = <&prci PRCI_CLK_PCLK>;
+			clocks = <&prci FU740_PRCI_CLK_PCLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -237,12 +237,12 @@
 			compatible = "sifive,fu540-c000-gem";
 			interrupt-parent = <&plic0>;
 			interrupts = <55>;
-			reg = <0x0 0x10090000 0x0 0x2000
+			reg = <0x0 0x10090000 0x0 0x2000>,
-			       0x0 0x100a0000 0x0 0x1000>;
+			      <0x0 0x100a0000 0x0 0x1000>;
 			local-mac-address = [00 00 00 00 00 00];
 			clock-names = "pclk", "hclk";
-			clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+			clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>,
-				 <&prci PRCI_CLK_GEMGXLPLL>;
+				 <&prci FU740_PRCI_CLK_GEMGXLPLL>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -251,8 +251,8 @@
 			compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
 			reg = <0x0 0x10020000 0x0 0x1000>;
 			interrupt-parent = <&plic0>;
-			interrupts = <44 45 46 47>;
+			interrupts = <44>, <45>, <46>, <47>;
-			clocks = <&prci PRCI_CLK_PCLK>;
+			clocks = <&prci FU740_PRCI_CLK_PCLK>;
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
@@ -260,8 +260,8 @@
 			compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
 			reg = <0x0 0x10021000 0x0 0x1000>;
 			interrupt-parent = <&plic0>;
-			interrupts = <48 49 50 51>;
+			interrupts = <48>, <49>, <50>, <51>;
-			clocks = <&prci PRCI_CLK_PCLK>;
+			clocks = <&prci FU740_PRCI_CLK_PCLK>;
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
@@ -273,7 +273,7 @@
 			cache-size = <2097152>;
 			cache-unified;
 			interrupt-parent = <&plic0>;
-			interrupts = <19 21 22 20>;
+			interrupts = <19>, <21>, <22>, <20>;
 			reg = <0x0 0x2010000 0x0 0x1000>;
 		};
 		gpio: gpio@10060000 {
@@ -287,28 +287,27 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
-			clocks = <&prci PRCI_CLK_PCLK>;
+			clocks = <&prci FU740_PRCI_CLK_PCLK>;
 			status = "disabled";
 		};
 		pcie@e00000000 {
-			#address-cells = <3>;
-			#interrupt-cells = <1>;
-			#num-lanes = <8>;
-			#size-cells = <2>;
 			compatible = "sifive,fu740-pcie";
-			reg = <0xe 0x00000000 0x1 0x0
+			#address-cells = <3>;
-			       0xd 0xf0000000 0x0 0x10000000
+			#size-cells = <2>;
-			       0x0 0x100d0000 0x0 0x1000>;
+			#interrupt-cells = <1>;
+			reg = <0xe 0x00000000 0x0 0x80000000>,
+			      <0xd 0xf0000000 0x0 0x10000000>,
+			      <0x0 0x100d0000 0x0 0x1000>;
 			reg-names = "dbi", "config", "mgmt";
 			device_type = "pci";
 			dma-coherent;
 			bus-range = <0x0 0xff>;
-			ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000
+			ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000>,      /* I/O */
-				  0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000
+				 <0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000>,    /* mem */
-				  0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000
+				 <0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000>,    /* mem */
-				  0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;
+				 <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
 			num-lanes = <0x8>;
-			interrupts = <56 57 58 59 60 61 62 63 64>;
+			interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
 			interrupt-names = "msi", "inta", "intb", "intc", "intd";
 			interrupt-parent = <&plic0>;
 			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
@@ -316,13 +315,11 @@
 					<0x0 0x0 0x0 0x2 &plic0 58>,
 					<0x0 0x0 0x0 0x3 &plic0 59>,
 					<0x0 0x0 0x0 0x4 &plic0 60>;
+			clock-names = "pcie_aux";
+			clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
 			pwren-gpios = <&gpio 5 0>;
 			reset-gpios = <&gpio 8 0>;
-			clocks = <&prci PRCI_CLK_PCIEAUX>;
+			resets = <&prci 4>;
-			clock-names = "pcieaux";
-			resets = <&prci PRCI_RST_PCIE_POWER_UP_N>;
-			reset-names = "rst_n";
-
 			status = "okay";
 		};
 	};

arch/riscv/dts/hifive-unmatched-a00.dts

@@ -1,5 +1,5 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2019-2021 SiFive, Inc */
+/* Copyright (c) 2020 SiFive, Inc */
 
 #include "fu740-c000.dtsi"
 #include <dt-bindings/gpio/gpio.h>
@@ -9,8 +9,6 @@
 #define RTCCLK_FREQ		1000000
 
 / {
-	#address-cells = <2>;
-	#size-cells = <2>;
 	model = "SiFive HiFive Unmatched A00";
 	compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
 		     "sifive,fu740";
@@ -28,9 +26,6 @@
 		reg = <0x0 0x80000000 0x4 0x00000000>;
 	};
 
-	soc {
-	};
-
 	hfclk: hfclk {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
@@ -65,10 +60,21 @@
 	temperature-sensor@4c {
 		compatible = "ti,tmp451";
 		reg = <0x4c>;
+		vcc-supply = <&vdd_bpro>;
 		interrupt-parent = <&gpio>;
 		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
 	};
 
+	eeprom@54 {
+		compatible = "microchip,24c02", "atmel,24c02";
+		reg = <0x54>;
+		vcc-supply = <&vdd_bpro>;
+		label = "board-id";
+		pagesize = <16>;
+		read-only;
+		size = <256>;
+	};
+
 	pmic@58 {
 		compatible = "dlg,da9063";
 		reg = <0x58>;
@@ -76,48 +82,44 @@
 		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
 		interrupt-controller;
 
-		regulators {
+		onkey {
-			vdd_bcore1: bcore1 {
+			compatible = "dlg,da9063-onkey";
-				regulator-min-microvolt = <1050000>;
-				regulator-max-microvolt = <1050000>;
-				regulator-min-microamp = <5000000>;
-				regulator-max-microamp = <5000000>;
-				regulator-always-on;
 		};
 
-			vdd_bcore2: bcore2 {
+		rtc {
+			compatible = "dlg,da9063-rtc";
+		};
+
+		wdt {
+			compatible = "dlg,da9063-watchdog";
+		};
+
+		regulators {
+			vdd_bcore: bcores-merged {
 				regulator-min-microvolt = <1050000>;
 				regulator-max-microvolt = <1050000>;
-				regulator-min-microamp = <5000000>;
+				regulator-min-microamp = <4800000>;
-				regulator-max-microamp = <5000000>;
+				regulator-max-microamp = <4800000>;
 				regulator-always-on;
 			};
 
 			vdd_bpro: bpro {
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
-				regulator-min-microamp = <2500000>;
+				regulator-min-microamp = <2400000>;
-				regulator-max-microamp = <2500000>;
+				regulator-max-microamp = <2400000>;
 				regulator-always-on;
 			};
 
 			vdd_bperi: bperi {
-				regulator-min-microvolt = <1050000>;
+				regulator-min-microvolt = <1060000>;
-				regulator-max-microvolt = <1050000>;
+				regulator-max-microvolt = <1060000>;
 				regulator-min-microamp = <1500000>;
 				regulator-max-microamp = <1500000>;
 				regulator-always-on;
 			};
 
-			vdd_bmem: bmem {
+			vdd_bmem_bio: bmem-bio-merged {
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-min-microamp = <3000000>;
-				regulator-max-microamp = <3000000>;
-				regulator-always-on;
-			};
-
-			vdd_bio: bio {
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <1200000>;
 				regulator-min-microamp = <3000000>;
@@ -128,86 +130,66 @@
 			vdd_ldo1: ldo1 {
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
-				regulator-min-microamp = <100000>;
-				regulator-max-microamp = <100000>;
 				regulator-always-on;
 			};
 
 			vdd_ldo2: ldo2 {
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
-				regulator-min-microamp = <200000>;
-				regulator-max-microamp = <200000>;
 				regulator-always-on;
 			};
 
 			vdd_ldo3: ldo3 {
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
-				regulator-min-microamp = <200000>;
-				regulator-max-microamp = <200000>;
 				regulator-always-on;
 			};
 
 			vdd_ldo4: ldo4 {
 				regulator-min-microvolt = <2500000>;
 				regulator-max-microvolt = <2500000>;
-				regulator-min-microamp = <200000>;
-				regulator-max-microamp = <200000>;
 				regulator-always-on;
 			};
 
 			vdd_ldo5: ldo5 {
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
-				regulator-min-microamp = <100000>;
-				regulator-max-microamp = <100000>;
 				regulator-always-on;
 			};
 
 			vdd_ldo6: ldo6 {
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
-				regulator-min-microamp = <200000>;
-				regulator-max-microamp = <200000>;
 				regulator-always-on;
 			};
 
 			vdd_ldo7: ldo7 {
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
-				regulator-min-microamp = <200000>;
-				regulator-max-microamp = <200000>;
 				regulator-always-on;
 			};
 
 			vdd_ldo8: ldo8 {
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
-				regulator-min-microamp = <200000>;
-				regulator-max-microamp = <200000>;
 				regulator-always-on;
 			};
 
 			vdd_ld09: ldo9 {
 				regulator-min-microvolt = <1050000>;
 				regulator-max-microvolt = <1050000>;
-				regulator-min-microamp = <200000>;
+				regulator-always-on;
-				regulator-max-microamp = <200000>;
 			};
 
 			vdd_ldo10: ldo10 {
 				regulator-min-microvolt = <1000000>;
 				regulator-max-microvolt = <1000000>;
-				regulator-min-microamp = <300000>;
+				regulator-always-on;
-				regulator-max-microamp = <300000>;
 			};
 
 			vdd_ldo11: ldo11 {
 				regulator-min-microvolt = <2500000>;
 				regulator-max-microvolt = <2500000>;
-				regulator-min-microamp = <300000>;
-				regulator-max-microamp = <300000>;
 				regulator-always-on;
 			};
 		};
@@ -217,7 +199,7 @@
 &qspi0 {
 	status = "okay";
 	flash@0 {
-		compatible = "issi,is25wp256", "jedec,spi-nor";
+		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <50000000>;
 		m25p,fast-read;
@@ -234,6 +216,7 @@
 		spi-max-frequency = <20000000>;
 		voltage-ranges = <3300 3300>;
 		disable-wp;
+		gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -256,4 +239,8 @@
 
 &gpio {
 	status = "okay";
+	gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3",
+		"PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN",
+		"ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4",
+		"EN_VDD_SD", "SD_CD";
 };

board/CZ.NIC/turris_atsha_otp.c

@@ -93,30 +93,57 @@ int turris_atsha_otp_init_mac_addresses(int first_idx)
 	return 0;
 }
 
-int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num)
+int turris_atsha_otp_init_serial_number(void)
+{
+	char serial[17];
+	int ret;
+
+	ret = turris_atsha_otp_get_serial_number(serial);
+	if (ret)
+		return ret;
+
+	if (!env_get("serial#"))
+		return -1;
+
+	return 0;
+}
+
+int turris_atsha_otp_get_serial_number(char serial[17])
 {
 	struct udevice *dev = get_atsha204a_dev();
+	u32 version_num, serial_num;
+	const char *serial_env;
 	int ret;
 
 	if (!dev)
 		return -1;
 
+	serial_env = env_get("serial#");
+	if (serial_env && strlen(serial_env) == 16) {
+		memcpy(serial, serial_env, 17);
+		return 0;
+	}
+
 	ret = atsha204a_wakeup(dev);
 	if (ret)
 		return ret;
 
 	ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
 			     TURRIS_ATSHA_OTP_VERSION,
-			     (u8 *)version_num);
+			     (u8 *)&version_num);
 	if (ret)
 		return ret;
 
 	ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
 			     TURRIS_ATSHA_OTP_SERIAL,
-			     (u8 *)serial_num);
+			     (u8 *)&serial_num);
 	if (ret)
 		return ret;
 
 	atsha204a_sleep(dev);
+
+	sprintf(serial, "%08X%08X", be32_to_cpu(version_num), be32_to_cpu(serial_num));
+	env_set("serial#", serial);
+
 	return 0;
 }

board/CZ.NIC/turris_atsha_otp.h

@@ -4,6 +4,7 @@
 #define TURRIS_ATSHA_OTP_H
 
 int turris_atsha_otp_init_mac_addresses(int first_idx);
-int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num);
+int turris_atsha_otp_init_serial_number(void);
+int turris_atsha_otp_get_serial_number(char serial[17]);
 
 #endif

board/CZ.NIC/turris_mox/turris_mox.c

@@ -23,6 +23,7 @@
 #include <linux/string.h>
 #include <miiphy.h>
 #include <spi.h>
+#include <spi_flash.h>
 
 #include "mox_sp.h"
 
@@ -339,6 +340,51 @@ static int get_reset_gpio(struct gpio_desc *reset_gpio)
 	return 0;
 }
 
+/* Load default system DTB binary to $fdr_addr */
+static void load_spi_dtb(void)
+{
+	const char *const env_name[1] = { "fdt_addr" };
+	unsigned long size, offset;
+	struct udevice *spi_dev;
+	struct spi_flash *flash;
+	const char *addr_str;
+	unsigned long addr;
+	void *buf;
+
+	addr_str = env_get(env_name[0]);
+	if (!addr_str) {
+		env_set_default_vars(1, (char * const *)env_name, 0);
+		addr_str = env_get(env_name[0]);
+	}
+
+	if (!addr_str)
+		return;
+
+	addr = hextoul(addr_str, NULL);
+	if (!addr)
+		return;
+
+	spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, &spi_dev);
+	flash = dev_get_uclass_priv(spi_dev);
+	if (!flash)
+		return;
+
+	/*
+	 * SPI NOR "dtb" partition offset & size hardcoded for now because the
+	 * mtd subsystem does not offer finding the partition yet and we do not
+	 * want to reimplement OF partition parser here.
+	 */
+	offset = 0x7f0000;
+	size = 0x10000;
+
+	buf = map_physmem(addr, size, MAP_WRBACK);
+	if (!buf)
+		return;
+
+	spi_flash_read(flash, offset, size, buf);
+	unmap_physmem(buf, size);
+}
+
 int misc_init_r(void)
 {
 	u8 mac[2][6];
@@ -358,6 +404,8 @@ int misc_init_r(void)
 			eth_env_set_enetaddr_by_index("eth", i, mac[i]);
 	}
 
+	load_spi_dtb();
+
 	return 0;
 }
 
@@ -440,8 +488,9 @@ static void handle_reset_button(void)
 	env_set_default_vars(1, (char * const *)vars, 0);
 
 	if (read_reset_button()) {
-		const char * const vars[2] = {
+		const char * const vars[3] = {
 			"bootcmd",
+			"bootdelay",
 			"distro_bootcmd",
 		};
 
@@ -449,7 +498,7 @@ static void handle_reset_button(void)
 		 * Set the above envs to their default values, in case the user
 		 * managed to break them.
 		 */
-		env_set_default_vars(2, (char * const *)vars, 0);
+		env_set_default_vars(3, (char * const *)vars, 0);
 
 		/* Ensure bootcmd_rescue is used by distroboot */
 		env_set("boot_targets", "rescue");

board/CZ.NIC/turris_omnia/turris_omnia.c

@@ -549,8 +549,9 @@ static void handle_reset_button(void)
 	env_set_ulong("omnia_reset", reset_status);
 
 	if (reset_status) {
-		const char * const vars[2] = {
+		const char * const vars[3] = {
 			"bootcmd",
+			"bootdelay",
 			"distro_bootcmd",
 		};
 
@@ -558,7 +559,7 @@ static void handle_reset_button(void)
 		 * Set the above envs to their default values, in case the user
 		 * managed to break them.
 		 */
-		env_set_default_vars(2, (char * const *)vars, 0);
+		env_set_default_vars(3, (char * const *)vars, 0);
 
 		/* Ensure bootcmd_rescue is used by distroboot */
 		env_set("boot_targets", "rescue");
@@ -653,7 +654,7 @@ static void initialize_switch(void)
 	ctrl[1] = EXT_CTL_nRES_LAN;
 	err = omnia_mcu_write(CMD_EXT_CONTROL, ctrl, sizeof(ctrl));
 
-	mdelay(10);
+	mdelay(50);
 
 	/* Change RGMII pins back to RGMII mode */
 
@@ -963,19 +964,15 @@ int board_late_init(void)
 
 int show_board_info(void)
 {
-	u32 version_num, serial_num;
+	char serial[17];
 	int err;
 
-	err = turris_atsha_otp_get_serial_number(&version_num, &serial_num);
+	err = turris_atsha_otp_get_serial_number(serial);
 	printf("Model: Turris Omnia\n");
 	printf("  MCU type: %s\n", omnia_get_mcu_type());
 	printf("  MCU version: %s\n", omnia_get_mcu_version());
 	printf("  RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
-	if (err)
+	printf("  Serial Number: %s\n", !err ? serial : "unknown");
-		printf("  Serial Number: unknown\n");
-	else
-		printf("  Serial Number: %08X%08X\n", be32_to_cpu(version_num),
-		       be32_to_cpu(serial_num));
 
 	return 0;
 }
@@ -983,6 +980,7 @@ int show_board_info(void)
 int misc_init_r(void)
 {
 	turris_atsha_otp_init_mac_addresses(1);
+	turris_atsha_otp_init_serial_number();
 	return 0;
 }
 

board/Marvell/mvebu_armada-37xx/board.c

@@ -132,6 +132,8 @@ int board_late_init(void)
 		dev = mmc_dev->dev;
 		device_remove(dev, DM_REMOVE_NORMAL);
 		device_unbind(dev);
+		if (of_live_active())
+			ofnode_set_enabled(dev_ofnode(dev), false);
 	}
 
 	/* Ensure that 'env default -a' set correct value to $fdtfile */

board/bsh/imx6ulz_smm_m2/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_MX6ULZ_SMM_M2
+
+config SYS_BOARD
+	default "imx6ulz_smm_m2"
+
+config SYS_VENDOR
+	default "bsh"
+
+config SYS_CONFIG_NAME
+	default "imx6ulz_smm_m2"
+
+endif

board/bsh/imx6ulz_smm_m2/MAINTAINERS

@@ -0,0 +1,6 @@
+MX6ULZ_SMM_M2 BOARD
+M:	Michael Trimarchi <michael@amarulasolutions.com>
+S:	Maintained
+F:	board/bsh/mx6ulz_smm_m2/
+F:	include/configs/imx6ulz_smm_m2.h
+F:	configs/imx6ulz_smm_m2_defconfig

board/bsh/imx6ulz_smm_m2/Makefile

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2021 Amarula Solutions B.V.
+
+obj-y  := imx6ulz_smm_m2.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
+

board/bsh/imx6ulz_smm_m2/README

@@ -0,0 +1,67 @@
+How to Update U-Boot on imx6ulz_smm_m2 board
+--------------------------------------------
+
+Required software on the host PC:
+
+- UUU: https://github.com/NXPmicro/mfgtools
+
+Build U-Boot for m2:
+
+$ make mrproper
+$ make imx6ulz_smm_m2_defconfig
+$ make
+
+This generates the SPL and u-boot-dtb.img binaries.
+
+1. Loading U-Boot via USB Serial Download Protocol
+
+Copy SPL and u-boot-dtb.img to the uuu folder.
+
+Load the U-Boot via USB:
+
+$ sudo uuu -v -b nand_script.lst u-boot-with-spl.imx
+
+where nand_script.lst contains the following:
+
+uuu_version 1.2.39
+
+# @_flash.bin            | bootloader
+# @_image   [_flash.bin] | image burn to nand, default is the same as bootloader
+
+# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ
+SDP: boot -f _flash.bin
+
+# This command will be run when ROM support stream mode
+# i.MX8QXP, i.MX8QM
+SDPS: boot -f _flash.bin
+
+# These commands will be run when use SPL and will be skipped if no spl
+# SDPU will be deprecated. please use SDPV instead of SDPU
+# {
+SDPU: delay 1000
+SDPU: write -f _flash.bin -offset 0x57c00
+SDPU: jump
+# }
+
+# These commands will be run when use SPL and will be skipped if no spl
+# if (SPL support SDPV)
+# {
+SDPV: delay 1000
+SDPV: write -f _flash.bin -offset 0x11000
+SDPV: jump
+# }
+
+FB: ucmd setenv fastboot_buffer ${loadaddr}
+FB: download -f _image
+FB: ucmd if test ! -n "$fastboot_bytes"; then setenv fastboot_bytes $filesize; else true; fi
+# Burn image to nandfit partition if needed
+FB: ucmd if env exists nandfit_part; then nand erase.part nandfit; nand write ${fastboot_buffer} nandfit ${fastboot_bytes}; else true; fi;
+FB: ucmd nandbcb init ${fastboot_buffer} nandboot ${fastboot_bytes}
+FB: Done
+
+Then U-Boot starts and its messages appear in the console program.
+
+Use the default environment variables:
+
+=> env default -f -a
+=> saveenv

board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c

@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Copyright (C) 2021 BSH Hausgeraete GmbH
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <common.h>
+#include <env.h>
+#include <linux/sizes.h>
+
+static void setup_gpmi_nand(void)
+{
+	setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			   MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			   MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
+};
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_gpmi_nand();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	if (is_boot_from_usb()) {
+		env_set("bootcmd", "run bootcmd_mfg");
+		env_set("bootdelay", "0");
+	}
+
+	return 0;
+}

board/bsh/imx6ulz_smm_m2/spl.c

@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ull_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <linux/libfdt.h>
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+		       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+		       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static const iomux_v3_cfg_t uart4_pads[] = {
+	MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds		= 0x00000028,
+	.grp_ddrmode_ctl	= 0x00020000,
+	.grp_b0ds		= 0x00000028,
+	.grp_ctlds		= 0x00000028,
+	.grp_b1ds		= 0x00000028,
+	.grp_ddrpke		= 0x00000000,
+	.grp_ddrmode		= 0x00020000,
+	.grp_ddr_type		= 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0		= 0x00000028,
+	.dram_dqm1		= 0x00000028,
+	.dram_ras		= 0x00000028,
+	.dram_cas		= 0x00000028,
+	.dram_odt0		= 0x00000028,
+	.dram_odt1		= 0x00000028,
+	.dram_sdba2		= 0x00000000,
+	.dram_sdclk_0		= 0x00000028,
+	.dram_sdqs0		= 0x00000028,
+	.dram_sdqs1		= 0x00000028,
+	.dram_reset		= 0x000c0028,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0		= 0x00000000,
+	.p0_mpwldectrl1		= 0x00100010,
+	.p0_mpdgctrl0		= 0x414c014c,
+	.p0_mpdgctrl1		= 0x00000000,
+	.p0_mprddlctl		= 0x40403a42,
+	.p0_mpwrdlctl		= 0x4040342e,
+};
+
+static struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize			= 0,
+	.cs1_mirror		= 0,
+	.cs_density		= 32,
+	.ncs			= 1,
+	.bi_on			= 1,
+	.rtt_nom		= 1,
+	.rtt_wr			= 0,
+	.ralat			= 5,
+	.walat			= 1,
+	.mif3_mode		= 3,
+	.rst_to_cke		= 0x23,	/* 33 cycles (JEDEC value for DDR3) - total of 500 us */
+	.sde_to_rst		= 0x10,	/* 14 cycles (JEDEC value for DDR3) - total of 200 us */
+	.refsel			= 1,
+	.refr			= 3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed		= 1333,
+	.density		= 2,
+	.width			= 16,
+	.banks			= 8,
+	.rowaddr		= 13,
+	.coladdr		= 10,
+	.pagesz			= 2,
+	.trcd			= 1350,
+	.trcmin			= 4950,
+	.trasmin		= 3600,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+}
+
+static void imx6ul_spl_dram_cfg(void)
+{
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+	arch_cpu_init();
+	timer_init();
+	setup_iomux_uart();
+	preloader_console_init();
+	imx6ul_spl_dram_cfg();
+}
+
+void reset_cpu(void)
+{
+}

board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c

@@ -22,7 +22,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d4000d4, 0x940000 },
 	{ 0x3d4000dc, 0xd4002d },
 	{ 0x3d4000e0, 0x310000 },
-	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000e8, 0x36004d },
 	{ 0x3d4000ec, 0x16004d },
 	{ 0x3d400100, 0x191e1920 },
 	{ 0x3d400104, 0x60630 },
@@ -55,6 +55,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400204, 0x80808 },
 	{ 0x3d400214, 0x7070707 },
 	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
 	{ 0x3d400250, 0x29001701 },
 	{ 0x3d400254, 0x2c },
 	{ 0x3d40025c, 0x4000030 },
@@ -72,7 +73,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d402064, 0xc001c },
 	{ 0x3d4020dc, 0x840000 },
 	{ 0x3d4020e0, 0x310000 },
-	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020e8, 0x36004d },
 	{ 0x3d4020ec, 0x16004d },
 	{ 0x3d402100, 0xa040305 },
 	{ 0x3d402104, 0x30407 },
@@ -97,7 +98,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d403064, 0x30007 },
 	{ 0x3d4030dc, 0x840000 },
 	{ 0x3d4030e0, 0x310000 },
-	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030e8, 0x36004d },
 	{ 0x3d4030ec, 0x16004d },
 	{ 0x3d403100, 0xa010102 },
 	{ 0x3d403104, 0x30404 },
@@ -1059,25 +1060,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0x54012, 0x110 },
 	{ 0x54019, 0x2dd4 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x1 },
 	{ 0x54032, 0xd400 },
 	{ 0x54033, 0x312d },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
 	{ 0x54039, 0x312d },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1098,25 +1099,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{ 0x54012, 0x110 },
 	{ 0x54019, 0x84 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x84 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x1 },
 	{ 0x54032, 0x8400 },
 	{ 0x54033, 0x3100 },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0x8400 },
 	{ 0x54039, 0x3100 },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1137,25 +1138,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
 	{ 0x54012, 0x110 },
 	{ 0x54019, 0x84 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x84 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x1 },
 	{ 0x54032, 0x8400 },
 	{ 0x54033, 0x3100 },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0x8400 },
 	{ 0x54039, 0x3100 },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1177,25 +1178,25 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0x54012, 0x110 },
 	{ 0x54019, 0x2dd4 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x1 },
 	{ 0x54032, 0xd400 },
 	{ 0x54033, 0x312d },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
 	{ 0x54039, 0x312d },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1692,15 +1693,15 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{ 0x400d6, 0x20a },
 	{ 0x400d7, 0x20b },
 	{ 0x2003a, 0x2 },
-	{ 0x2000b, 0x5d },
+	{ 0x2000b, 0x34b },
 	{ 0x2000c, 0xbb },
 	{ 0x2000d, 0x753 },
 	{ 0x2000e, 0x2c },
-	{ 0x12000b, 0xc },
+	{ 0x12000b, 0x70 },
 	{ 0x12000c, 0x19 },
 	{ 0x12000d, 0xfa },
 	{ 0x12000e, 0x10 },
-	{ 0x22000b, 0x3 },
+	{ 0x22000b, 0x1c },
 	{ 0x22000c, 0x6 },
 	{ 0x22000d, 0x3e },
 	{ 0x22000e, 0x10 },

board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c

@@ -22,7 +22,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d4000d4, 0x940000 },
 	{ 0x3d4000dc, 0xd4002d },
 	{ 0x3d4000e0, 0x310000 },
-	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000e8, 0x36004d },
 	{ 0x3d4000ec, 0x16004d },
 	{ 0x3d400100, 0x191e1920 },
 	{ 0x3d400104, 0x60630 },
@@ -55,6 +55,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400204, 0x80808 },
 	{ 0x3d400214, 0x7070707 },
 	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
 	{ 0x3d400250, 0x29001701 },
 	{ 0x3d400254, 0x2c },
 	{ 0x3d40025c, 0x4000030 },
@@ -72,7 +73,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d402064, 0xc001c },
 	{ 0x3d4020dc, 0x840000 },
 	{ 0x3d4020e0, 0x310000 },
-	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020e8, 0x36004d },
 	{ 0x3d4020ec, 0x16004d },
 	{ 0x3d402100, 0xa040305 },
 	{ 0x3d402104, 0x30407 },
@@ -1059,25 +1060,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0x54012, 0x310 },
 	{ 0x54019, 0x2dd4 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
 	{ 0x54032, 0xd400 },
 	{ 0x54033, 0x312d },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
 	{ 0x54039, 0x312d },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1098,25 +1099,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{ 0x54012, 0x310 },
 	{ 0x54019, 0x84 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x84 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
 	{ 0x54032, 0x8400 },
 	{ 0x54033, 0x3100 },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0x8400 },
 	{ 0x54039, 0x3100 },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1172,31 +1173,30 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0x54008, 0x61 },
 	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400d, 0x100 },
 	{ 0x5400f, 0x100 },
 	{ 0x54010, 0x1f7f },
 	{ 0x54012, 0x310 },
 	{ 0x54019, 0x2dd4 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
 	{ 0x54032, 0xd400 },
 	{ 0x54033, 0x312d },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
 	{ 0x54039, 0x312d },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1693,15 +1693,15 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{ 0x400d6, 0x20a },
 	{ 0x400d7, 0x20b },
 	{ 0x2003a, 0x2 },
-	{ 0x2000b, 0x5d },
+	{ 0x2000b, 0x34b },
 	{ 0x2000c, 0xbb },
 	{ 0x2000d, 0x753 },
 	{ 0x2000e, 0x2c },
-	{ 0x12000b, 0xc },
+	{ 0x12000b, 0x70 },
 	{ 0x12000c, 0x19 },
 	{ 0x12000d, 0xfa },
 	{ 0x12000e, 0x10 },
-	{ 0x22000b, 0x3 },
+	{ 0x22000b, 0x1c },
 	{ 0x22000c, 0x6 },
 	{ 0x22000d, 0x3e },
 	{ 0x22000e, 0x10 },
@@ -1715,6 +1715,10 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{ 0x90013, 0x6152 },
 	{ 0x20010, 0x5a },
 	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
 	{ 0x40080, 0xe0 },
 	{ 0x40081, 0x12 },
 	{ 0x40082, 0xe0 },

board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c

@@ -1799,8 +1799,8 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 
 static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 	{
-		/* P0 3732mts 1D */
+		/* P0 3733mts 1D */
-		.drate = 3732,
+		.drate = 3733,
 		.fw_type = FW_1D_IMAGE,
 		.fsp_cfg = ddr_fsp0_cfg,
 		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@@ -1820,8 +1820,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
 	},
 	{
-		/* P0 3732mts 2D */
+		/* P0 3733mts 2D */
-		.drate = 3732,
+		.drate = 3733,
 		.fw_type = FW_2D_IMAGE,
 		.fsp_cfg = ddr_fsp0_2d_cfg,
 		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@@ -1840,5 +1840,5 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32 = {
 	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
 	.ddrphy_pie = ddr_phy_pie,
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
-	.fsp_table = { 3732, 400, 100, },
+	.fsp_table = { 3733, 400, 100, },
 };

board/dhelectronics/dh_stm32mp1/board.c

@@ -527,56 +527,6 @@ static void sysconf_init(void)
 #endif
 }
 
-static void board_init_fmc2(void)
-{
-#define STM32_FMC2_BCR1			0x0
-#define STM32_FMC2_BTR1			0x4
-#define STM32_FMC2_BWTR1		0x104
-#define STM32_FMC2_BCR(x)		((x) * 0x8 + STM32_FMC2_BCR1)
-#define STM32_FMC2_BCRx_FMCEN		BIT(31)
-#define STM32_FMC2_BCRx_WREN		BIT(12)
-#define STM32_FMC2_BCRx_RSVD		BIT(7)
-#define STM32_FMC2_BCRx_FACCEN		BIT(6)
-#define STM32_FMC2_BCRx_MWID(n)		((n) << 4)
-#define STM32_FMC2_BCRx_MTYP(n)		((n) << 2)
-#define STM32_FMC2_BCRx_MUXEN		BIT(1)
-#define STM32_FMC2_BCRx_MBKEN		BIT(0)
-#define STM32_FMC2_BTR(x)		((x) * 0x8 + STM32_FMC2_BTR1)
-#define STM32_FMC2_BTRx_DATAHLD(n)	((n) << 30)
-#define STM32_FMC2_BTRx_BUSTURN(n)	((n) << 16)
-#define STM32_FMC2_BTRx_DATAST(n)	((n) << 8)
-#define STM32_FMC2_BTRx_ADDHLD(n)	((n) << 4)
-#define STM32_FMC2_BTRx_ADDSET(n)	((n) << 0)
-
-#define RCC_MP_AHB6RSTCLRR		0x218
-#define RCC_MP_AHB6RSTCLRR_FMCRST	BIT(12)
-#define RCC_MP_AHB6ENSETR		0x19c
-#define RCC_MP_AHB6ENSETR_FMCEN		BIT(12)
-
-	const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
-			STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
-			STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
-			STM32_FMC2_BCRx_MBKEN;
-	const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
-			STM32_FMC2_BTRx_BUSTURN(2) |
-			STM32_FMC2_BTRx_DATAST(0x22) |
-			STM32_FMC2_BTRx_ADDHLD(2) |
-			STM32_FMC2_BTRx_ADDSET(2);
-
-	/* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
-	writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
-	writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
-
-	/* KS8851-16MLL -- Muxed mode */
-	writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
-	writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
-	/* AS7C34098 SRAM on X11 -- Muxed mode */
-	writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
-	writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
-
-	setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
-}
-
 #ifdef CONFIG_DM_REGULATOR
 #define STPMIC_NVM_BUCKS_VOUT_SHR			0xfc
 #define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V2		0
@@ -671,8 +621,6 @@ int board_init(void)
 
 	sysconf_init();
 
-	board_init_fmc2();
-
 	return 0;
 }
 

board/firefly/firefly-rk3308/roc_cc_rk3308.c

@@ -70,7 +70,7 @@ int rockchip_dnl_key_pressed(void)
 {
 	unsigned int val;
 
-	if (adc_channel_single_shot("saradc", 1, &val)) {
+	if (adc_channel_single_shot("saradc@ff1e0000", 1, &val)) {
 		printf("%s read adc key val failed\n", __func__);
 		return false;
 	}

board/freescale/imxrt1170-evk/Kconfig

@@ -0,0 +1,22 @@
+if TARGET_IMXRT1170_EVK
+
+config SYS_BOARD
+	string
+	default "imxrt1170-evk"
+
+config SYS_VENDOR
+	string
+	default "freescale"
+
+config SYS_SOC
+	string
+	default "imxrt1170"
+
+config SYS_CONFIG_NAME
+	string
+	default "imxrt1170-evk"
+
+config IMX_CONFIG
+	default "board/freescale/imxrt1170-evk/imximage.cfg"
+
+endif

board/freescale/imxrt1170-evk/MAINTAINERS

@@ -0,0 +1,7 @@
+IMXRT1170 EVALUATION KIT
+M:	Giulio Benetti <giulio.benetti@benettiengineering.com>
+M:	Jesse Taube <Mr.Bossman075@gmail.com>
+S:	Maintained
+F:	board/freescale/imxrt1170-evk
+F:	include/configs/imxrt1170-evk.h
+F:	configs/imxrt1170-evk_defconfig

board/freescale/imxrt1170-evk/Makefile

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+
+obj-y	:= imxrt1170-evk.o

board/freescale/imxrt1170-evk/imximage.cfg

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
+ * Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */

board/freescale/imxrt1170-evk/imxrt1170-evk.c

@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SUPPORT_SPL
+	int rv;
+	struct udevice *dev;
+
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv) {
+		debug("DRAM init failed: %d\n", rv);
+		return rv;
+	}
+
+#endif
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	debug("SPL: booting kernel\n");
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+int spl_dram_init(void)
+{
+	struct udevice *dev;
+	int rv;
+
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv)
+		debug("DRAM init failed: %d\n", rv);
+	return rv;
+}
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+	spl_dram_init();
+	arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_MMC1;
+}
+#endif
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+	return 0;
+}

board/freescale/ls1043ardb/ddr.c

@@ -114,7 +114,7 @@ dimm_params_t ddr_raw_timing = {
 	.mirrored_dimm = 0,
 	.n_row_addr = 15,
 	.n_col_addr = 10,
-	.bank_addr_bits = 0,
+	.bank_addr_bits = 2,
 	.bank_group_bits = 2,
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,

board/freescale/p1_p2_rdb_pc/README

@@ -60,5 +60,5 @@ enabled in relative defconfig file,
    CONFIG_RESET_VECTOR_ADDRESS - 0xffc
 
 If device tree support is enabled in defconfig,
-1. use 'u-boot-with-dtb.bin' for NOR boot.
+1. use 'u-boot.bin' for NOR boot.
 2. use 'u-boot-with-spl.bin' for other boot.