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m68k: add mcf5307 cpu support
Add Freescale MCF5307 cpu support. Signed-off-by: Angelo Dureghello <angelo@sysam.it>
This commit is contained in:
angelo@sysam.it
Tom Rini
parent
06fd66a4aa
commit
e77e65dfc2
12 changed files with 742 additions and 2 deletions
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@ -15,7 +15,8 @@
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#define CONFIG_CF_V2
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#endif
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#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x)
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#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
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defined(CONFIG_MCF5301x)
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#define CONFIG_CF_V3
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#endif
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@ -240,6 +240,30 @@
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#endif
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#endif /* CONFIG_M5282 */
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#ifdef CONFIG_M5307
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#include <asm/immap_5307.h>
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#include <asm/m5307.h>
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#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
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(CONFIG_SYS_UART_PORT * 0x40))
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#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
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#define CONFIG_SYS_NUM_IRQS (64)
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
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#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
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#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \
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(CONFIG_SYS_INTR_BASE))->ipr)
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#define CONFIG_SYS_TMRINTR_NO (31)
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#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
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#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
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#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
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MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
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#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#endif /* CONFIG_M5307 */
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#if defined(CONFIG_MCF5301x)
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#include <asm/immap_5301x.h>
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#include <asm/m5301x.h>
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118
arch/m68k/include/asm/immap_5307.h
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118
arch/m68k/include/asm/immap_5307.h
Normal file
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@ -0,0 +1,118 @@
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/*
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* (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __IMMAP_5307__
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#define __IMMAP_5307__
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#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000)
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#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
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#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080)
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#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100)
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#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
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#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
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#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
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#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
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#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244)
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typedef struct sim {
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u8 rsr;
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u8 sypcr;
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u8 swivr;
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u8 swsr;
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u16 par;
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u8 irqpar;
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u8 res1;
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u8 pllcr;
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u8 res2;
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u16 res3;
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u8 mpark;
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u8 res4;
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u16 res5;
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u32 res6;
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} sim_t;
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typedef struct intctrl {
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u32 ipr;
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u32 imr;
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u16 res7;
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u8 res8;
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u8 avr;
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u8 icr0;
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u8 icr1;
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u8 icr2;
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u8 icr3;
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u8 icr4;
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u8 icr5;
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u8 icr6;
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u8 icr7;
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u8 icr8;
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u8 icr9;
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u16 res9;
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} intctrl_t;
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typedef struct csm {
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u16 csar0; /* Chip-select Address */
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u16 res1;
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u32 csmr0; /* Chip-select Mask */
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u16 res2;
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u16 cscr0; /* Chip-select Control */
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u16 csar1;
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u16 res3;
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u32 csmr1;
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u16 res4;
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u16 cscr1;
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u16 csar2;
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u16 res5;
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u32 csmr2;
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u16 res6;
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u16 cscr2;
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u16 csar3;
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u16 res7;
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u32 csmr3;
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u16 res8;
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u16 cscr3;
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u16 csar4;
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u16 res9;
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u32 csmr4;
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u16 res10;
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u16 cscr4;
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u16 csar5;
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u16 res11;
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u32 csmr5;
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u16 res12;
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u16 cscr5;
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u16 csar6;
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u16 res13;
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u32 csmr6;
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u16 res14;
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u16 cscr6;
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u16 csar7;
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u16 res15;
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u32 csmr7;
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u16 res16;
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u16 cscr7;
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} csm_t;
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typedef struct sdramctrl {
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u16 dcr;
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u16 res1;
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u32 res2;
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u32 dacr0;
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u32 dmr0;
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u32 dacr1;
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u32 dmr1;
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} sdramctrl_t;
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typedef struct gpio {
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u16 paddr;
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u16 res1;
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u16 padat;
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u16 res2;
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} gpio_t;
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#endif /* __IMMAP_5307__ */
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70
arch/m68k/include/asm/m5307.h
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70
arch/m68k/include/asm/m5307.h
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@ -0,0 +1,70 @@
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/*
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* (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef mcf5307_h
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#define mcf5307_h
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/*
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* Size of internal RAM (RAMBAR)
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*/
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#define INT_RAM_SIZE 4096
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/* Bit definitions and macros for SYPCR */
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#define SYPCR_SWTAVAL 0x02
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#define SYPCR_SWTA 0x04
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#define SYPCR_SWT(x) ((x&0x3)<<3)
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#define SYPCR_SWP 0x20
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#define SYPCR_SWRI 0x40
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#define SYPCR_SWE 0x80
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/* Bit definitions and macros for CSMR */
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#define CSMR_V 0x01
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#define CSMR_UD 0x02
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#define CSMR_UC 0x04
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#define CSMR_SD 0x08
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#define CSMR_SC 0x10
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#define CSMR_CI 0x20
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#define CSMR_AM 0x40
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#define CSMR_WP 0x100
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/* Bit definitions and macros for DACR (SDRAM) */
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#define DACR_PM_CONTINUOUS 0x04
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#define DACR_IP_PRECHG_ALL 0x08
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#define DACR_PORT_SZ_32 0
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#define DACR_PORT_SZ_8 (1<<4)
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#define DACR_PORT_SZ_16 (2<<4)
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#define DACR_IMRS_INIT_CMD (1<<6)
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#define DACR_CMD_PIN(x) ((x&7)<<8)
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#define DACR_CASL(x) ((x&3)<<12)
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#define DACR_RE (1<<15)
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/* Bit definitions and macros for CSCR */
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#define CSCR_BSTW 0x08
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#define CSCR_BSTR 0x10
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#define CSCR_BEM 0x20
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#define CSCR_PS(x) ((x&0x3)<<6)
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#define CSCR_AA 0x100
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#define CSCR_WS ((x&0xf)<<10)
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/* Bit definitions for the ICR family of registers */
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#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
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#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
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#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
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#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
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#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
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#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
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#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
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#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
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#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
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#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
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#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
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#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
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#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
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#endif /* mcf5307_h */
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@ -17,7 +17,8 @@
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/****************************************************************************/
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/* DMA Timer module registers */
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typedef struct dtimer_ctrl {
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272)
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
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defined(CONFIG_M5272) || defined(CONFIG_M5307)
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u16 tmr; /* 0x00 Mode register */
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u16 res1; /* 0x02 */
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u16 trr; /* 0x04 Reference register */
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