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Merge patch series "Add fdt-fixups for AM62P variants"
Aparna Patra <a-patra@ti.com> says: This series implements fdt fixups, by reading hardware information from registers and accordingly delete/modify the DT nodes, at run-time. Logs for AM62P boot: https://gist.github.com/itsme-aparna/b889fe59882c1acf0ef25a644bd325c4 Link: https://lore.kernel.org/r/20250108044939.392785-1-a-patra@ti.com
This commit is contained in:
Tom Rini
commit
e26a9ac4c6
3 changed files with 210 additions and 0 deletions
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@ -7,8 +7,91 @@
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#include "../common_fdt.h"
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#include <fdt_support.h>
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static void fdt_fixup_cores_wdt_nodes_am62p(void *blob, int core_nr)
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{
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char node_path[32];
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if (core_nr < 1)
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return;
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for (; core_nr < 4; core_nr++) {
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snprintf(node_path, sizeof(node_path), "/cpus/cpu@%d", core_nr);
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fdt_del_node_path(blob, node_path);
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snprintf(node_path, sizeof(node_path), "/cpus/cpu-map/cluster0/core%d", core_nr);
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fdt_del_node_path(blob, node_path);
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snprintf(node_path, sizeof(node_path), "/bus@f0000/watchdog@e0%d0000", core_nr);
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fdt_del_node_path(blob, node_path);
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}
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}
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static void fdt_fixup_video_codec_nodes_am62p(void *blob, bool has_video_codec)
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{
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if (!has_video_codec)
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fdt_del_node_path(blob, "/bus@f0000/video-codec@30210000");
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}
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static void fdt_fixup_canfd_nodes_am62p(void *blob, bool has_canfd)
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{
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if (!has_canfd) {
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fdt_del_node_path(blob, "/bus@f0000/can@20701000");
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fdt_del_node_path(blob, "/bus@f0000/can@20711000");
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}
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}
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static int fdt_fixup_trips_node(void *blob, int zoneoffset, int maxc)
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{
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int node, trip;
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node = fdt_subnode_offset(blob, zoneoffset, "trips");
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if (node < 0)
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return -1;
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fdt_for_each_subnode(trip, blob, node) {
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const char *type = fdt_getprop(blob, trip, "type", NULL);
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if (!type || (strncmp(type, "critical", 8) != 0))
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continue;
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if (fdt_setprop_u32(blob, trip, "temperature", 1000 * maxc) < 0)
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return -1;
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}
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return 0;
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}
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static void fdt_fixup_thermal_zone_nodes_am62p(void *blob, int maxc)
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{
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int node, zone;
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node = fdt_path_offset(blob, "/thermal-zones");
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if (node < 0)
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return;
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fdt_for_each_subnode(zone, blob, node) {
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if (fdt_fixup_trips_node(blob, zone, maxc) < 0)
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printf("Failed to set temperature in %s critical trips\n",
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fdt_get_name(blob, zone, NULL));
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}
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}
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static void fdt_fixup_cpu_freq_nodes_am62p(void *blob, int max_freq)
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{
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if (max_freq >= 1250000000)
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return;
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if (max_freq <= 1000000000) {
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fdt_del_node_path(blob, "/opp-table/opp-1250000000");
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fdt_del_node_path(blob, "/opp-table/opp-1400000000");
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}
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}
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int ft_system_setup(void *blob, struct bd_info *bd)
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{
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fdt_fixup_cores_wdt_nodes_am62p(blob, k3_get_core_nr());
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fdt_fixup_video_codec_nodes_am62p(blob, k3_has_video_codec());
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fdt_fixup_canfd_nodes_am62p(blob, k3_has_canfd());
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fdt_fixup_thermal_zone_nodes_am62p(blob, k3_get_max_temp());
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fdt_fixup_cpu_freq_nodes_am62p(blob, k3_get_a53_max_frequency());
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fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000);
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fdt_fixup_reserved(blob, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000);
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@ -11,10 +11,14 @@
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#include <dm.h>
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#include <dm/uclass-internal.h>
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#include <dm/pinctrl.h>
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#include <dm/ofnode.h>
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#include "../sysfw-loader.h"
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#include "../common.h"
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/* TISCI DEV ID for A53 Clock */
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#define AM62PX_DEV_A53SS0_CORE_0_DEV_ID 135
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struct fwl_data cbass_main_fwls[] = {
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{ "FSS_DAT_REG3", 7, 8 },
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};
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@ -67,6 +71,62 @@ static void ctrl_mmr_unlock(void)
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mmr_unlock(PADCFG_MMR1_BASE, 1);
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}
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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static int get_a53_cpu_clock_index(ofnode node)
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{
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int count, i;
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struct ofnode_phandle_args *args;
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ofnode clknode;
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clknode = ofnode_path("/bus@f0000/system-controller@44043000/clock-controller");
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if (!ofnode_valid(clknode))
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return -1;
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count = ofnode_count_phandle_with_args(node, "assigned-clocks", "#clock-cells", 0);
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for (i = 0; i < count; i++) {
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if (!ofnode_parse_phandle_with_args(node, "assigned-clocks",
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"#clock-cells", 0, i, args)) {
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if (ofnode_equal(clknode, args->node) &&
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args->args[0] == AM62PX_DEV_A53SS0_CORE_0_DEV_ID)
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return i;
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}
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}
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return -1;
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}
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static void fixup_a53_cpu_freq_by_speed_grade(void)
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{
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int index, size;
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u32 *rates;
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ofnode node;
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node = ofnode_path("/a53@0");
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if (!ofnode_valid(node))
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return;
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rates = fdt_getprop_w(ofnode_to_fdt(node), ofnode_to_offset(node),
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"assigned-clock-rates", &size);
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index = get_a53_cpu_clock_index(node);
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if (!rates || index < 0 || index >= (size / sizeof(u32))) {
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printf("Wrong A53 assigned-clocks configuration\n");
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return;
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}
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rates[index] = cpu_to_fdt32(k3_get_a53_max_frequency());
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printf("Changed A53 CPU frequency to %dHz (%c grade) in DT\n",
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k3_get_a53_max_frequency(), k3_get_speed_grade());
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}
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#else
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static void fixup_a53_cpu_freq_by_speed_grade(void)
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{
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}
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#endif
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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@ -162,6 +222,8 @@ void board_init_f(ulong dummy)
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setup_qos();
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debug("am62px_init: %s done\n", __func__);
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fixup_a53_cpu_freq_by_speed_grade();
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}
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u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
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@ -19,6 +19,22 @@
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#define MCU_CTRL_MMR0_BASE 0x04500000
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#define WKUP_CTRL_MMR0_BASE 0x43000000
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#define CTRLMMR_WKUP_JTAG_DEVICE_ID (WKUP_CTRL_MMR0_BASE + 0x18)
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#define JTAG_DEV_CORE_NR_MASK GENMASK(19, 18)
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#define JTAG_DEV_CORE_NR_SHIFT 18
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#define JTAG_DEV_CANFD_MASK BIT(15)
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#define JTAG_DEV_CANFD_SHIFT 15
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#define JTAG_DEV_VIDEO_CODEC_MASK BIT(14)
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#define JTAG_DEV_VIDEO_CODEC_SHIFT 14
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#define JTAG_DEV_SPEED_MASK GENMASK(10, 6)
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#define JTAG_DEV_SPEED_SHIFT 6
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#define JTAG_DEV_TEMP_MASK GENMASK(5, 3)
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#define JTAG_DEV_TEMP_SHIFT 3
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#define JTAG_DEV_TEMP_AUTOMOTIVE 0x5
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#define JTAG_DEV_TEMP_EXTENDED_VALUE 105
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#define JTAG_DEV_TEMP_AUTOMOTIVE_VALUE 125
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#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
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@ -72,6 +88,55 @@
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#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
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static inline int k3_get_core_nr(void)
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{
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u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
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return ((dev_id & JTAG_DEV_CORE_NR_MASK) >> JTAG_DEV_CORE_NR_SHIFT) + 1;
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}
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static inline int k3_has_video_codec(void)
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{
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u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
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return !((dev_id & JTAG_DEV_VIDEO_CODEC_MASK) >> JTAG_DEV_VIDEO_CODEC_SHIFT);
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}
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static inline int k3_has_canfd(void)
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{
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u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
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return (dev_id & JTAG_DEV_CANFD_MASK) >> JTAG_DEV_CANFD_SHIFT;
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}
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static inline int k3_get_max_temp(void)
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{
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u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
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u32 dev_temp = (dev_id & JTAG_DEV_TEMP_MASK) >> JTAG_DEV_TEMP_SHIFT;
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if (dev_temp == JTAG_DEV_TEMP_AUTOMOTIVE)
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return JTAG_DEV_TEMP_AUTOMOTIVE_VALUE;
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else
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return JTAG_DEV_TEMP_EXTENDED_VALUE;
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}
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static inline char k3_get_speed_grade(void)
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{
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u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
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u32 speed_grade = (dev_id & JTAG_DEV_SPEED_MASK) >>
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JTAG_DEV_SPEED_SHIFT;
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return 'A' - 1 + speed_grade;
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}
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static inline int k3_get_a53_max_frequency(void)
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{
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if (k3_get_speed_grade() == 'O')
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return 1000000000;
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else
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return 1250000000;
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}
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#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
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static const u32 put_device_ids[] = {};
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