Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-04-17 18:34:42 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Xilinx changes for v2024.01-rc3

Browse source 
xilinx:
 - Disable lock in mini spi configurations
 
 zynq:
 - DTS syncups
 - Kconfig updates
 
 zynqmp:
 - DTS syncups
 - Kconfig fixups
 
 versal:
 - Make 30MHz as default freq for spi
 
 versal net:
 - Enable ADMA for mmc
 
 serial:
 - Read baudrate from DT
 
 spi:
 - Put spi lock under one Kconfig
 - Support 64bit addresses in cadance_ospi
 - zynqmp_gqspi - change logging support
 
 firmware:
 - Handle errors in zynqmp_pm_feature()
 
 include:
 - Sync vsc8531 dt binding with kernel
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCZUpXJQAKCRDKSWXLKUoM
 IWyDAJ4tgFIiBZ7fDfQhSzWVgrKjKO900wCePQS61G0662wUl2fiCzQeTzTfYl4=
 =VvHj
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2024.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2024.01-rc3

xilinx:
- Disable lock in mini spi configurations

zynq:
- DTS syncups
- Kconfig updates

zynqmp:
- DTS syncups
- Kconfig fixups

versal:
- Make 30MHz as default freq for spi

versal net:
- Enable ADMA for mmc

serial:
- Read baudrate from DT

spi:
- Put spi lock under one Kconfig
- Support 64bit addresses in cadance_ospi
- zynqmp_gqspi - change logging support

firmware:
- Handle errors in zynqmp_pm_feature()

include:
- Sync vsc8531 dt binding with kernel
This commit is contained in:
Tom Rini 2023-11-07 10:36:23 -05:00
commit e17d174773
78 changed files with 1138 additions and 145 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

27
arch/arm/dts/Makefile
View file

@ -376,6 +376,12 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cse-nand.dtb \
zynq-cse-nor.dtb \
zynq-cse-qspi-single.dtb \
zynq-cse-qspi-parallel.dtb \
zynq-cse-qspi-stacked.dtb \
zynq-cse-qspi-x1-single.dtb \
zynq-cse-qspi-x1-stacked.dtb \
zynq-cse-qspi-x2-single.dtb \
zynq-cse-qspi-x2-stacked.dtb \
zynq-dlc20-rev1.0.dtb \
zynq-microzed.dtb \
zynq-minized.dtb \
@ -417,6 +423,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
zynqmp-mini-qspi.dtb \
zynqmp-mini-qspi-parallel.dtb \
zynqmp-mini-qspi-single.dtb \
zynqmp-mini-qspi-stacked.dtb \
zynqmp-mini-qspi-x1-single.dtb \
zynqmp-mini-qspi-x1-stacked.dtb \
zynqmp-mini-qspi-x2-single.dtb \
zynqmp-mini-qspi-x2-stacked.dtb \
zynqmp-sc-revB.dtb \
zynqmp-sc-revC.dtb \
zynqmp-sc-vek280-revA.dtbo \
@ -467,13 +480,27 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
versal-mini-emmc0.dtb \
versal-mini-emmc1.dtb \
versal-mini-ospi-single.dtb \
versal-mini-ospi-stacked.dtb \
versal-mini-qspi-parallel.dtb \
versal-mini-qspi-single.dtb \
versal-mini-qspi-stacked.dtb \
versal-mini-qspi-x1-single.dtb \
versal-mini-qspi-x1-stacked.dtb \
versal-mini-qspi-x2-single.dtb \
versal-mini-qspi-x2-stacked.dtb \
xilinx-versal-virt.dtb
dtb-$(CONFIG_ARCH_VERSAL_NET) += \
versal-net-mini.dtb \
versal-net-mini-emmc.dtb \
versal-net-mini-ospi-single.dtb \
versal-net-mini-ospi-stacked.dtb \
versal-net-mini-qspi-single.dtb \
versal-net-mini-qspi-parallel.dtb \
versal-net-mini-qspi-stacked.dtb \
versal-net-mini-qspi-x1-single.dtb \
versal-net-mini-qspi-x1-stacked.dtb \
versal-net-mini-qspi-x2-single.dtb \
versal-net-mini-qspi-x2-stacked.dtb \
xilinx-versal-net-virt.dtb
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
zynqmp-r5.dtb

2
arch/arm/dts/bitmain-antminer-s9.dts
View file

@ -52,6 +52,8 @@
&nfc0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
};

22
arch/arm/dts/versal-mini-ospi-stacked.dts Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal QSPI Quad Stacked DTS
*
* Copyright (C) 2018-2020 Xilinx, Inc.
*/
#include "versal-mini-ospi.dtsi"
/ {
model = "Xilinx Versal MINI OSPI STACKED";
};
&ospi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-rx-bus-width = <8>;
};

22
arch/arm/dts/versal-mini-qspi-parallel.dts Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal QSPI Quad Parallel DTS
*
* Copyright (C) 2018-2019 Xilinx, Inc.
*/
#include "versal-mini-qspi.dtsi"
/ {
model = "Xilinx Versal MINI QSPI PARALLEL";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-rx-bus-width = <4>;
};

22
arch/arm/dts/versal-mini-qspi-stacked.dts Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal QSPI Quad Stacked DTS
*
* Copyright (C) 2018-2019 Xilinx, Inc.
*/
#include "versal-mini-qspi.dtsi"
/ {
model = "Xilinx Versal MINI QSPI STACKED";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-rx-bus-width = <4>;
};

17
arch/arm/dts/versal-mini-qspi-x1-single.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal QSPI x1 Single DTS
*
* Copyright (C) 2018-2019 Xilinx, Inc.
*/
#include "versal-mini-qspi.dtsi"
/ {
model = "Xilinx Versal MINI QSPI X1 SINGLE";
};
&flash0 {
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};

23
arch/arm/dts/versal-mini-qspi-x1-stacked.dts Normal file
View file

@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal QSPI x1 Stacked DTS
*
* Copyright (C) 2018-2019 Xilinx, Inc.
*/
#include "versal-mini-qspi.dtsi"
/ {
model = "Xilinx Versal MINI QSPI X1 STACKED";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};

17
arch/arm/dts/versal-mini-qspi-x2-single.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal QSPI x2 Single DTS
*
* Copyright (C) 2018-2019 Xilinx, Inc.
*/
#include "versal-mini-qspi.dtsi"
/ {
model = "Xilinx Versal MINI QSPI X2 SINGLE";
};
&flash0 {
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};

23
arch/arm/dts/versal-mini-qspi-x2-stacked.dts Normal file
View file

@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal QSPI x2 Stacked DTS
*
* Copyright (C) 2018-2019 Xilinx, Inc.
*/
#include "versal-mini-qspi.dtsi"
/ {
model = "Xilinx Versal MINI QSPI X2 STACKED";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};

22
arch/arm/dts/versal-net-mini-ospi-stacked.dts Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET OSPI Quad Stacked DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-ospi.dtsi"
/ {
model = "Xilinx Versal NET MINI OSPI STACKED";
};
&ospi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-rx-bus-width = <8>;
};

22
arch/arm/dts/versal-net-mini-qspi-parallel.dts Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI Quad Parallel DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI PARALLEL";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-rx-bus-width = <4>;
};

22
arch/arm/dts/versal-net-mini-qspi-stacked.dts Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI Quad Stacked DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI STACKED";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-rx-bus-width = <4>;
};

17
arch/arm/dts/versal-net-mini-qspi-x1-single.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI x1 Single DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI X1 SINGLE";
};
&flash0 {
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};

23
arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts Normal file
View file

@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI x1 Stacked DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI X1 STACKED";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};

17
arch/arm/dts/versal-net-mini-qspi-x2-single.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI x2 Single DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI X2 SINGLE";
};
&flash0 {
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};

23
arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts Normal file
View file

@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal NET QSPI x2 Stacked DTS
*
* (C) Copyright 2023, Advanced Micro Devices, Inc.
*/
#include "versal-net-mini-qspi.dtsi"
/ {
model = "Xilinx Versal NET MINI QSPI X2 STACKED";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};

4
arch/arm/dts/zynq-7000.dtsi
View file

@ -306,15 +306,11 @@
compatible = "arm,pl353-nand-r2p1";
reg = <0 0 0x1000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
nor0: flash@1,0 {
status = "disabled";
compatible = "cfi-flash";
reg = <1 0 0x2000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};

22
arch/arm/dts/zynq-cse-qspi-parallel.dts Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI Quad Parallel DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynq-cse-qspi.dtsi"
/ {
model = "Zynq CSE QSPI PARALLEL Board";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-rx-bus-width = <4>;
};

22
arch/arm/dts/zynq-cse-qspi-stacked.dts Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI Quad Stacked DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynq-cse-qspi.dtsi"
/ {
model = "Zynq CSE QSPI STACKED Board";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-rx-bus-width = <4>;
};

16
arch/arm/dts/zynq-cse-qspi-x1-single.dts Normal file
View file

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI x1 Single DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynq-cse-qspi.dtsi"
/ {
model = "Zynq CSE QSPI X1 SINGLE Board";
};
&flash0 {
spi-rx-bus-width = <1>;
};

22
arch/arm/dts/zynq-cse-qspi-x1-stacked.dts Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI x1 Stacked DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynq-cse-qspi.dtsi"
/ {
model = "Zynq CSE QSPI X1 STACKED Board";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-rx-bus-width = <1>;
};

16
arch/arm/dts/zynq-cse-qspi-x2-single.dts Normal file
View file

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI x2 Single DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynq-cse-qspi.dtsi"
/ {
model = "Zynq CSE QSPI X2 SINGLE Board";
};
&flash0 {
spi-rx-bus-width = <2>;
};

22
arch/arm/dts/zynq-cse-qspi-x2-stacked.dts Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI x2 Stacked DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynq-cse-qspi.dtsi"
/ {
model = "Zynq CSE QSPI X2 STACKED Board";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-rx-bus-width = <2>;
};

25
arch/arm/dts/zynq-zc702.dts
View file

@ -406,6 +406,31 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 {
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
partition@c00000 {
label = "qspi-bitstream";
reg = <0xc00000 0x400000>;
};
};
};
};

30
arch/arm/dts/zynq-zc706.dts
View file

@ -309,13 +309,39 @@
&qspi {
bootph-all;
status = "okay";
num-cs = <1>;
num-cs = <2>;
flash@0 {
compatible = "n25q128a11", "jedec,spi-nor";
reg = <0x0>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 {
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
partition@c00000 {
label = "qspi-bitstream";
reg = <0xc00000 0x400000>;
};
};
};
};

25
arch/arm/dts/zynq-zc770-xm010.dts
View file

@ -69,6 +69,31 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 {
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
partition@c00000 {
label = "qspi-bitstream";
reg = <0xc00000 0x400000>;
};
};
};
};

19
arch/arm/dts/zynq-zc770-xm011.dts
View file

@ -49,8 +49,27 @@
&nfc0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "nand-fsbl-uboot";
reg = <0x0 0x1000000>;
};
partition@1000000 {
label = "nand-linux";
reg = <0x1000000 0x2000000>;
};
partition@3000000 {
label = "nand-rootfs";
reg = <0x3000000 0x200000>;
};
};
};
};

25
arch/arm/dts/zynq-zc770-xm012.dts
View file

@ -56,6 +56,31 @@
&nor0 {
status = "okay";
bank-width = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "nor-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "nor-linux";
reg = <0x100000 0x500000>;
};
partition@600000 {
label = "nor-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 {
label = "nor-rootfs";
reg = <0x620000 0x5e0000>;
};
partition@c00000 {
label = "nor-bitstream";
reg = <0xc00000 0x400000>;
};
};
};
&smcc {

30
arch/arm/dts/zynq-zc770-xm013.dts
View file

@ -61,13 +61,39 @@
&qspi {
status = "okay";
num-cs = <1>;
num-cs = <2>;
flash@0 {
compatible = "n25q128a11", "jedec,spi-nor";
reg = <0x0>;
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 {
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
partition@c00000 {
label = "qspi-bitstream";
reg = <0xc00000 0x400000>;
};
};
};
};

29
arch/arm/dts/zynq-zed.dts
View file

@ -55,8 +55,35 @@
flash@0 {
compatible = "spansion,s25fl256s1", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <30000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@600000 {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@620000 {
label = "qspi-rootfs";
reg = <0x620000 0x5e0000>;
};
partition@c00000 {
label = "qspi-bitstream";
reg = <0xc00000 0x400000>;
};
};
};
};

6
arch/arm/dts/zynqmp-clk-ccf.dtsi
View file

@ -10,12 +10,6 @@
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
/ {
fclk0: fclk0 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <&zynqmp_clk PL0_REF>;
};
pss_ref_clk: pss_ref_clk {
bootph-all;
compatible = "fixed-clock";

4
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
View file

@ -71,11 +71,13 @@
&qspi {
status = "okay";
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;

4
arch/arm/dts/zynqmp-m-a2197-02-revA.dts
View file

@ -67,11 +67,13 @@
&qspi {
status = "okay";
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;

4
arch/arm/dts/zynqmp-m-a2197-03-revA.dts
View file

@ -67,11 +67,13 @@
&qspi {
status = "okay";
num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;

21
arch/arm/dts/zynqmp-mini-qspi-parallel.dts Normal file
View file

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZynqMP QSPI Quad Parallel DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynqmp-mini-qspi.dts"
/ {
model = "ZynqMP MINI QSPI PARALLEL";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
};

12
arch/arm/dts/zynqmp-mini-qspi-single.dts Normal file
View file

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZynqMP QSPI single DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynqmp-mini-qspi.dts"
/ {
model = "ZynqMP MINI QSPI SINGLE";
};

21
arch/arm/dts/zynqmp-mini-qspi-stacked.dts Normal file
View file

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZynqMP QSPI Quad Stacked DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynqmp-mini-qspi.dts"
/ {
model = "ZynqMP MINI QSPI STACKED";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
};

17
arch/arm/dts/zynqmp-mini-qspi-x1-single.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZynqMP QSPI x1 Single DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynqmp-mini-qspi.dts"
/ {
model = "ZynqMP MINI QSPI X1 SINGLE";
};
&flash0 {
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};

23
arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts Normal file
View file

@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZynqMP QSPI x1 Stacked DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynqmp-mini-qspi.dts"
/ {
model = "ZynqMP MINI QSPI X1 STACKED";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};

17
arch/arm/dts/zynqmp-mini-qspi-x2-single.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI x2 Single DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynqmp-mini-qspi.dts"
/ {
model = "ZynqMP MINI QSPI X2 SINGLE";
};
&flash0 {
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};

23
arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts Normal file
View file

@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZynqMP QSPI x2 Stacked DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynqmp-mini-qspi.dts"
/ {
model = "ZynqMP MINI QSPI X2 STACKED";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};

25
arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
View file

@ -190,6 +190,25 @@
&pinctrl0 {
status = "okay";
pinctrl_gpio0_default: gpio0-default {
conf {
groups = "gpio0_38_grp";
bias-pull-up;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_38_grp";
function = "gpio0";
};
conf-tx {
pins = "MIO38";
bias-disable;
output-enable;
};
};
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
@ -345,6 +364,12 @@
};
};
&gpio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";

25
arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
View file

@ -178,6 +178,25 @@
&pinctrl0 {
status = "okay";
pinctrl_gpio0_default: gpio0-default {
conf {
groups = "gpio0_38_grp";
bias-pull-up;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_38_grp";
function = "gpio0";
};
conf-tx {
pins = "MIO38";
bias-disable;
output-enable;
};
};
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
@ -333,6 +352,12 @@
};
};
&gpio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";

10
arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
View file

@ -119,9 +119,13 @@
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
phy0: ethernet-phy@0 { /* u131 - M88e1512 */
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
/* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
phy0: ethernet-phy@0 { /* u131 - M88e1512 */
reg = <0>;
};
};
};

10
arch/arm/dts/zynqmp-vpk120-revA.dts
View file

@ -120,9 +120,13 @@
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
phy0: ethernet-phy@0 {
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
/* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};

6
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
View file

@ -141,8 +141,7 @@
reg = <0x0>;
#address-cells = <0x2>;
#size-cells = <0x1>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-0";
nand-ecc-step-size = <1024>;
@ -178,8 +177,7 @@
reg = <0x1>;
#address-cells = <0x2>;
#size-cells = <0x1>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-1";
nand-ecc-step-size = <1024>;

117
arch/arm/dts/zynqmp.dtsi
View file

@ -214,16 +214,61 @@
soc_revision: soc-revision@0 {
reg = <0x0 0x4>;
};
/* efuse access */
efuse_dna: efuse-dna@c {
reg = <0xc 0xc>;
};
efuse_usr0: efuse-usr0@20 {
reg = <0x20 0x4>;
};
efuse_usr1: efuse-usr1@24 {
reg = <0x24 0x4>;
};
efuse_usr2: efuse-usr2@28 {
reg = <0x28 0x4>;
};
efuse_usr3: efuse-usr3@2c {
reg = <0x2c 0x4>;
};
efuse_usr4: efuse-usr4@30 {
reg = <0x30 0x4>;
};
efuse_usr5: efuse-usr5@34 {
reg = <0x34 0x4>;
};
efuse_usr6: efuse-usr6@38 {
reg = <0x38 0x4>;
};
efuse_usr7: efuse-usr7@3c {
reg = <0x3c 0x4>;
};
efuse_miscusr: efuse-miscusr@40 {
reg = <0x40 0x4>;
};
efuse_chash: efuse-chash@50 {
reg = <0x50 0x4>;
};
efuse_pufmisc: efuse-pufmisc@54 {
reg = <0x54 0x4>;
};
efuse_sec: efuse-sec@58 {
reg = <0x58 0x4>;
};
efuse_spkid: efuse-spkid@5c {
reg = <0x5c 0x4>;
};
efuse_ppk0hash: efuse-ppk0hash@a0 {
reg = <0xa0 0x30>;
};
efuse_ppk1hash: efuse-ppk1hash@d0 {
reg = <0xd0 0x30>;
};
};
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
xlnx_aes: zynqmp-aes {
compatible = "xlnx,zynqmp-aes";
};
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
@ -261,7 +306,6 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
power-domains = <&zynqmp_firmware PD_PL>;
};
remoteproc {
@ -344,7 +388,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14e8>;
/* iommus = <&smmu 0x14e8>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -357,7 +401,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14e9>;
/* iommus = <&smmu 0x14e9>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -370,7 +414,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ea>;
/* iommus = <&smmu 0x14ea>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -383,7 +427,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14eb>;
/* iommus = <&smmu 0x14eb>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -396,7 +440,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ec>;
/* iommus = <&smmu 0x14ec>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -409,7 +453,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ed>;
/* iommus = <&smmu 0x14ed>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -422,7 +466,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ee>;
/* iommus = <&smmu 0x14ee>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -435,7 +479,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ef>;
/* iommus = <&smmu 0x14ef>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -480,7 +524,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x868>;
/* iommus = <&smmu 0x868>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -493,7 +537,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x869>;
/* iommus = <&smmu 0x869>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -506,7 +550,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86a>;
/* iommus = <&smmu 0x86a>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -519,7 +563,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86b>;
/* iommus = <&smmu 0x86b>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -532,7 +576,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86c>;
/* iommus = <&smmu 0x86c>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -545,7 +589,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86d>;
/* iommus = <&smmu 0x86d>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -558,7 +602,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86e>;
/* iommus = <&smmu 0x86e>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -571,7 +615,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86f>;
/* iommus = <&smmu 0x86f>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -591,7 +635,7 @@
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
iommus = <&smmu 0x872>;
/* iommus = <&smmu 0x872>; */
power-domains = <&zynqmp_firmware PD_NAND>;
};
@ -603,7 +647,7 @@
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
iommus = <&smmu 0x874>;
/* iommus = <&smmu 0x874>; */
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
reset-names = "gem0_rst";
@ -617,7 +661,7 @@
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
iommus = <&smmu 0x875>;
/* iommus = <&smmu 0x875>; */
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
reset-names = "gem1_rst";
@ -631,7 +675,7 @@
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
iommus = <&smmu 0x876>;
/* iommus = <&smmu 0x876>; */
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
reset-names = "gem2_rst";
@ -645,7 +689,7 @@
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
iommus = <&smmu 0x877>;
/* iommus = <&smmu 0x877>; */
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
reset-names = "gem3_rst";
@ -724,7 +768,7 @@
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
iommus = <&smmu 0x4d0>;
/* iommus = <&smmu 0x4d0>; */
power-domains = <&zynqmp_firmware PD_PCIE>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
@ -745,7 +789,7 @@
<0x0 0xc0000000 0x0 0x8000000>;
#address-cells = <1>;
#size-cells = <0>;
iommus = <&smmu 0x873>;
/* iommus = <&smmu 0x873>; */
power-domains = <&zynqmp_firmware PD_QSPI>;
};
@ -777,8 +821,7 @@
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&zynqmp_firmware PD_SATA>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
<&smmu 0x4c2>, <&smmu 0x4c3>;
/* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
/* dma-coherent; */
};
@ -790,7 +833,7 @@
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
iommus = <&smmu 0x870>;
/* iommus = <&smmu 0x870>; */
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
power-domains = <&zynqmp_firmware PD_SD_0>;
@ -805,7 +848,7 @@
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
iommus = <&smmu 0x871>;
/* iommus = <&smmu 0x871>; */
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
power-domains = <&zynqmp_firmware PD_SD_1>;
@ -956,11 +999,10 @@
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu 0x860>;
/* iommus = <&smmu 0x860>; */
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
snps,enable_guctl1_ipd_quirk;
snps,xhci-stream-quirk;
snps,resume-hs-terminations;
/* dma-coherent; */
};
@ -989,11 +1031,10 @@
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu 0x861>;
/* iommus = <&smmu 0x861>; */
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
snps,enable_guctl1_ipd_quirk;
snps,xhci-stream-quirk;
snps,resume-hs-terminations;
/* dma-coherent; */
};
@ -1039,8 +1080,6 @@
compatible = "xlnx,zynqmp-ams-pl";
status = "disabled";
reg = <0x400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
};
};
@ -1052,6 +1091,7 @@
interrupt-parent = <&gic>;
clock-names = "axi_clk";
power-domains = <&zynqmp_firmware PD_DP>;
/* iommus = <&smmu 0xce4>; */
#dma-cells = <1>;
};
@ -1066,6 +1106,7 @@
reg-names = "dp", "blend", "av_buf", "aud";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
/* iommus = <&smmu 0xce3>; */
clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_vtc_pixel_clk_in";
power-domains = <&zynqmp_firmware PD_DP>;

24
arch/arm/mach-zynqmp/Kconfig
View file

@ -100,30 +100,30 @@ config SPL_ZYNQMP_DRAM_ECC_INIT
config SPL_ZYNQMP_DRAM_BANK1_BASE
depends on SPL_ZYNQMP_DRAM_ECC_INIT
hex "DRAM Bank1 address"
default 0x00000000
help
Start address of DRAM ECC bank1
default 0x00000000
help
Start address of DRAM ECC bank1
config SPL_ZYNQMP_DRAM_BANK1_LEN
depends on SPL_ZYNQMP_DRAM_ECC_INIT
hex "DRAM Bank1 size"
default 0x80000000
help
Size in bytes of the DRAM ECC bank1
default 0x80000000
help
Size in bytes of the DRAM ECC bank1
config SPL_ZYNQMP_DRAM_BANK2_BASE
depends on SPL_ZYNQMP_DRAM_ECC_INIT
hex "DRAM Bank2 address"
default 0x800000000
help
Start address of DRAM ECC bank2
default 0x800000000
help
Start address of DRAM ECC bank2
config SPL_ZYNQMP_DRAM_BANK2_LEN
depends on SPL_ZYNQMP_DRAM_ECC_INIT
hex "DRAM Bank2 size"
default 0x0
help
Size in bytes of the DRAM ECC bank2. A null size takes no action.
default 0x0
help
Size in bytes of the DRAM ECC bank2. A null size takes no action.
config SYS_MALLOC_F_LEN
default 0x600

1
arch/sandbox/dts/test.dts
View file

@ -1572,6 +1572,7 @@
other-node = "/some-bus/c-test@5";
int-values = <0x1937 72993>;
u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
stdout-path = "serial0:115200n8";
chosen-test {
compatible = "denx,u-boot-fdt-test";
reg = <9 1>;

4
cmd/sf.c
View file

@ -604,7 +604,7 @@ static int do_spi_flash(struct cmd_tbl *cmdtp, int flag, int argc,
ret = do_spi_flash_read_write(argc, argv);
else if (strcmp(cmd, "erase") == 0)
ret = do_spi_flash_erase(argc, argv);
else if (strcmp(cmd, "protect") == 0)
else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0)
ret = do_spi_protect(argc, argv);
else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test"))
ret = do_spi_flash_test(argc, argv);
@ -629,8 +629,10 @@ U_BOOT_LONGHELP(sf,
"sf update addr offset|partition len - erase and write `len' bytes from memory\n"
" at `addr' to flash at `offset'\n"
" or to start of mtd `partition'\n"
#ifdef CONFIG_SPI_FLASH_LOCK
"sf protect lock/unlock sector len - protect/unprotect 'len' bytes starting\n"
" at address 'sector'"
#endif
#ifdef CONFIG_CMD_SF_TEST
"\nsf test offset len - run a very basic destructive test"
#endif

1
configs/eDPU_defconfig
View file

@ -20,6 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DEFAULT_ENV_IS_RW=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="eDPU>> "

1
configs/mvebu_db-88f3720_defconfig
View file

@ -22,6 +22,7 @@ CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DEFAULT_ENV_IS_RW=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MAXARGS=32

1
configs/mvebu_espressobin-88f3720_defconfig
View file

@ -24,6 +24,7 @@ CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DEFAULT_ENV_IS_RW=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y

1
configs/uDPU_defconfig
View file

@ -20,6 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DEFAULT_ENV_IS_RW=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="uDPU>> "

1
configs/xilinx_versal_mini_ospi_defconfig
View file

@ -57,6 +57,7 @@ CONFIG_SYS_PROMPT="Versal> "
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
# CONFIG_SPI_FLASH_LOCK is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y

1
configs/xilinx_versal_mini_qspi_defconfig
View file

@ -61,6 +61,7 @@ CONFIG_SYS_PROMPT="Versal> "
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
# CONFIG_SPI_FLASH_LOCK is not set
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y

1
configs/xilinx_versal_net_mini_ospi_defconfig
View file

@ -56,6 +56,7 @@ CONFIG_SYS_PROMPT="Versal NET> "
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
# CONFIG_SPI_FLASH_LOCK is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y

1
configs/xilinx_versal_net_mini_qspi_defconfig
View file

@ -60,6 +60,7 @@ CONFIG_SYS_PROMPT="Versal NET> "
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
# CONFIG_SPI_FLASH_LOCK is not set
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y

1
configs/xilinx_versal_net_virt_defconfig
View file

@ -85,6 +85,7 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
CONFIG_MTD=y

1
configs/xilinx_versal_virt_defconfig
View file

@ -6,6 +6,7 @@ CONFIG_ARCH_VERSAL=y
CONFIG_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x100000
CONFIG_NR_DRAM_BANKS=36
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y

2
configs/xilinx_zynq_virt_defconfig
View file

@ -126,6 +126,8 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y

1
configs/xilinx_zynqmp_mini_qspi_defconfig
View file

@ -77,6 +77,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
# CONFIG_SPI_FLASH_LOCK is not set
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y

41
doc/README.serial_dt_baud Normal file
View file

@ -0,0 +1,41 @@
Fetch serial baudrate from DT
-----------------------------
To support fetching of baudrate from DT, the following is done:-
The baudrate configured in Kconfig symbol CONFIG_BAUDRATE is taken by default by serial.
If change of baudrate is required then the Kconfig symbol CONFIG_BAUDRATE needs to
changed and U-Boot recompilation is required or the U-Boot environment needs to be updated.
To avoid this, add support to fetch the baudrate directly from the device tree file and
update the environment.
The default environment stores the default baudrate value. When default baudrate and dtb
baudrate are not same glitches are seen on the serial.
So, the environment also needs to be updated with the dtb baudrate to avoid the glitches on
the serial which is enabled by OF_SERIAL_BAUD.
The Kconfig SPL_ENV_SUPPORT needs to be enabled to allow patching in SPL.
The Kconfig DEFAULT_ENV_IS_RW which is enabled by OF_SERIAL_BAUD with making the environment
writable.
The ofnode_read_baud() function parses and fetches the baudrate value from the DT. This value
is validated and updated to baudrate during serial init. Padding is added at the end of the
default environment and the dt baudrate is updated with the latest value.
Example:-
The serial port options are of the form "bbbbpnf", where "bbbb" is the baud rate, "p" is parity ("n", "o", or "e"),
"n" is number of bits, and "f" is flow control ("r" for RTS or omit it). Default is "115200n8".
chosen {
bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/ram0 rw init_fatal_sh=1";
stdout-path = "serial0:115200n8";
};
From the chosen node, stdout-path property is obtained as string.
stdout-path = "serial0:115200n8";
The string is parsed to get the baudrate 115200. This string is converted to integer and updated to the environment.

18
drivers/core/ofnode.c
View file

@ -991,6 +991,24 @@ ofnode ofnode_get_chosen_node(const char *name)
return ofnode_path(prop);
}
int ofnode_read_baud(void)
{
const char *str, *p;
u32 baud;
str = ofnode_read_chosen_string("stdout-path");
if (!str)
return -EINVAL;
/* Parse string serial0:115200n8 */
p = strchr(str, ':');
if (!p)
return -EINVAL;
baud = dectoul(p + 1, NULL);
return baud;
}
const void *ofnode_read_aliases_prop(const char *propname, int *sizep)
{
ofnode node;

2
drivers/firmware/firmware-zynqmp.c
View file

@ -203,6 +203,8 @@ int zynqmp_pm_feature(const u32 api_id)
/* Check feature check API version */
ret = xilinx_pm_request(PM_FEATURE_CHECK, api_id, 0, 0, 0,
ret_payload);
if (ret)
return ret;
/* Return feature check version */
return ret_payload[1] & FIRMWARE_VERSION_MASK;

7
drivers/mtd/spi/Kconfig
View file

@ -134,6 +134,13 @@ config SPI_FLASH_BAR
Bank/Extended address registers are used to access the flash
which has size > 16MiB in 3-byte addressing.
config SPI_FLASH_LOCK
bool "Enable the Locking feature"
default y
help
Enable the SPI flash lock support. By default this is set to y.
If you intend not to use the lock support you should say n here.
config SPI_FLASH_UNLOCK_ALL
bool "Unlock the entire SPI flash on u-boot startup"
default y

8
drivers/mtd/spi/spi-nor-core.c
View file

@ -1100,6 +1100,7 @@ static int spansion_erase_non_uniform(struct spi_nor *nor, u32 addr,
}
#endif
#if defined(CONFIG_SPI_FLASH_LOCK)
#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
/* Write status register and ensure bits in mask match written values */
static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
@ -1387,6 +1388,7 @@ static int stm_is_unlocked(struct spi_nor *nor, loff_t ofs, uint64_t len)
return stm_is_unlocked_sr(nor, ofs, len, status);
}
#endif /* CONFIG_SPI_FLASH_STMICRO */
#endif
static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
{
@ -1462,6 +1464,7 @@ read_err:
return ret;
}
#if defined(CONFIG_SPI_FLASH_LOCK)
#ifdef CONFIG_SPI_FLASH_SST
/*
* sst26 flash series has its own block protection implementation:
@ -1730,6 +1733,8 @@ sst_write_err:
return ret;
}
#endif
#endif
/*
* Write an address range to the nor chip. Data must be written in
* FLASH_PAGESIZE chunks. The address range may be any size provided
@ -4104,6 +4109,7 @@ int spi_nor_scan(struct spi_nor *nor)
mtd->_read = spi_nor_read;
mtd->_write = spi_nor_write;
#if defined(CONFIG_SPI_FLASH_LOCK)
#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
/* NOR protection support for STmicro/Micron chips and similar */
if (JEDEC_MFR(info) == SNOR_MFR_ST ||
@ -4127,7 +4133,7 @@ int spi_nor_scan(struct spi_nor *nor)
nor->flash_is_unlocked = sst26_is_unlocked;
}
#endif
#endif
if (info->flags & USE_FSR)
nor->flags |= SNOR_F_USE_FSR;
if (info->flags & SPI_NOR_HAS_TB)

15
drivers/serial/Kconfig
View file

@ -24,6 +24,21 @@ config BAUDRATE
in the SPL stage (most drivers) or for choosing a default baudrate
in the absence of an environment setting (serial_mxc.c).
config OF_SERIAL_BAUD
bool "Fetch serial baudrate from device tree"
depends on DM_SERIAL && SPL_ENV_SUPPORT
select DEFAULT_ENV_IS_RW
help
Select this to enable fetching and setting of the baudrate
configured in the DT. Replace the default baudrate with the DT
baudrate and also set it to the environment.
config DEFAULT_ENV_IS_RW
bool "Make default environment as writable"
help
Select this to enable to make default environment writable. This
allows modifying the default environment.
config REQUIRE_SERIAL_CONSOLE
bool "Require a serial port for console"
# Running without a serial console is not supported by the

49
drivers/serial/serial-uclass.c
View file

@ -155,12 +155,61 @@ static void serial_find_console_or_panic(void)
}
#endif /* CONFIG_SERIAL_PRESENT */
/**
* check_valid_baudrate() - Check whether baudrate is valid or not
*
* @baud: baud rate to check
* Return: 0 if OK, -ve on error
*/
static int check_valid_baudrate(int baud)
{
int i;
for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
if (baud == baudrate_table[i])
return 0;
}
return -EINVAL;
}
int fetch_baud_from_dtb(void)
{
int baud_value, ret;
baud_value = ofnode_read_baud();
ret = check_valid_baudrate(baud_value);
if (ret)
return ret;
return baud_value;
}
/* Called prior to relocation */
int serial_init(void)
{
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
serial_find_console_or_panic();
gd->flags |= GD_FLG_SERIAL_READY;
if (IS_ENABLED(CONFIG_OF_SERIAL_BAUD)) {
int ret = 0;
char *ptr = (char*)&default_environment[0];
/*
* Fetch the baudrate from the dtb and update the value in the
* default environment.
*/
ret = fetch_baud_from_dtb();
if (ret != -EINVAL && ret != -EFAULT) {
gd->baudrate = ret;
while (*ptr != '\0' && *(ptr + 1) != '\0')
ptr++;
ptr += 2;
sprintf(ptr, "baudrate=%d", gd->baudrate);
}
}
serial_setbrg();
#endif

4
drivers/spi/cadence_ospi_versal.c
View file

@ -44,8 +44,10 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
priv->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE);
writel(CQSPI_DFLT_DMA_PERIPH_CFG,
priv->regbase + CQSPI_REG_DMA_PERIPH_CFG);
writel((unsigned long)rxbuf, priv->regbase +
writel(lower_32_bits((unsigned long)rxbuf), priv->regbase +
CQSPI_DMA_DST_ADDR_REG);
writel(upper_32_bits((unsigned long)rxbuf), priv->regbase +
CQSPI_DMA_DST_ADDR_MSB_REG);
writel(priv->trigger_address, priv->regbase +
CQSPI_DMA_SRC_RD_ADDR_REG);
writel(bytes_to_dma, priv->regbase +

82
drivers/spi/zynqmp_gqspi.c
View file

@ -5,6 +5,8 @@
* Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
*/
#define LOG_CATEGORY UCLASS_SPI
#include <common.h>
#include <cpu_func.h>
#include <log.h>
@ -192,8 +194,6 @@ static int zynqmp_qspi_of_to_plat(struct udevice *bus)
{
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
debug("%s\n", __func__);
plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) +
GQSPI_REG_OFFSET);
plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
@ -250,7 +250,7 @@ static u32 zynqmp_qspi_genfifo_mode(u8 buswidth)
case 4:
return GQSPI_SPI_MODE_QSPI;
default:
debug("Unsupported bus width %u\n", buswidth);
log_warning("Unsupported bus width %u\n", buswidth);
return GQSPI_SPI_MODE_SPI;
}
}
@ -262,6 +262,8 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
u32 config_reg, ier;
int ret = 0;
log_content("%s, GFIFO_CMD: 0x%X\n", __func__, gqspi_fifo_reg);
writel(gqspi_fifo_reg, &regs->genfifo);
config_reg = readl(&regs->confr);
@ -278,7 +280,7 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
GQSPI_TIMEOUT, 1);
if (ret)
printf("%s Timeout\n", __func__);
log_warning("%s, Timeout\n", __func__);
}
@ -286,6 +288,8 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
{
u32 gqspi_fifo_reg = 0;
log_debug("%s, assert: %d\r\n", __func__, is_on);
if (is_on) {
gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
@ -295,8 +299,6 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
}
debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
}
@ -311,8 +313,8 @@ static void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
clk_rate = plat->frequency;
reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
__func__, reqhz, clk_rate, baudrateval);
log_debug("%s, clk_rate:%d, baudrateval:%d, bus_clk: %d\n",
__func__, clk_rate, baudrateval, reqhz);
if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) ||
IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) {
@ -362,7 +364,8 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
u32 confr;
u8 baud_rate_val = 0;
debug("%s\n", __func__);
log_debug("%s, Speed: %d, Max: %d\n", __func__, speed, plat->frequency);
if (speed > plat->frequency)
speed = plat->frequency;
@ -383,9 +386,8 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
confr &= ~GQSPI_BAUD_DIV_MASK;
confr |= (baud_rate_val << 3);
writel(confr, &regs->confr);
zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
}
return 0;
@ -399,8 +401,6 @@ static int zynqmp_qspi_probe(struct udevice *bus)
unsigned long clock;
int ret;
debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
priv->regs = plat->regs;
priv->dma_regs = plat->dma_regs;
priv->io_mode = plat->io_mode;
@ -416,7 +416,6 @@ static int zynqmp_qspi_probe(struct udevice *bus)
dev_err(bus, "failed to get rate\n");
return clock;
}
debug("%s: CLK %ld\n", __func__, clock);
ret = clk_enable(&clk);
if (ret) {
@ -429,6 +428,8 @@ static int zynqmp_qspi_probe(struct udevice *bus)
/* init the zynq spi hw */
zynqmp_qspi_init_hw(priv);
log_debug("%s, Rerence clock frequency: %ld\n", __func__, clock);
return 0;
}
@ -438,7 +439,8 @@ static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
struct zynqmp_qspi_regs *regs = priv->regs;
u32 confr;
debug("%s\n", __func__);
log_debug("%s, 0x%X\n", __func__, mode);
/* Set the SPI Clock phase and polarities */
confr = readl(&regs->confr);
confr &= ~(GQSPI_CONFIG_CPHA_MASK | GQSPI_CONFIG_CPOL_MASK);
@ -461,16 +463,11 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
u32 *buf = (u32 *)priv->tx_buf;
u32 len = size;
debug("TxFIFO: 0x%x, size: 0x%x\n", readl(&regs->isr),
size);
while (size) {
ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXNFULL_MASK, 1,
GQSPI_TIMEOUT, 1);
if (ret) {
printf("%s: Timeout\n", __func__);
return ret;
}
if (ret)
return log_msg_ret("Timeout\n", ret);
if (size >= 4) {
writel(*buf, &regs->txd0r);
@ -501,10 +498,8 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1,
GQSPI_TIMEOUT, 1);
if (ret) {
printf("%s: Timeout\n", __func__);
return ret;
}
if (ret)
return log_msg_ret("Timeout\n", ret);
priv->tx_buf += len;
return 0;
@ -516,6 +511,9 @@ static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
u32 gen_fifo_cmd;
u8 i, dummy_cycles, addr;
log_debug("%s, opcode: 0x%0X, addr.nbytes: %d, dummy.mbytes: %d\r\n",
__func__, op->cmd.opcode, op->addr.nbytes, op->dummy.nbytes);
/* Send opcode */
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth);
@ -532,8 +530,6 @@ static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
gen_fifo_cmd |= GQSPI_GFIFO_TX;
gen_fifo_cmd |= addr;
debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
}
@ -583,6 +579,8 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
u32 len;
int ret = 0;
log_debug("%s, length: %d\r\n", __func__, priv->len);
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK;
@ -591,8 +589,6 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
ret = zynqmp_qspi_fill_tx_fifo(priv, 1 << len);
else
@ -608,7 +604,6 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv,
u32 gen_fifo_cmd, u32 *buf)
{
u32 len;
u32 actuallen = priv->len;
u32 config_reg, ier, isr;
u32 timeout = GQSPI_TIMEOUT;
struct zynqmp_qspi_regs *regs = priv->regs;
@ -623,7 +618,7 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv,
else
priv->bytes_to_receive = len;
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
/* Manual start */
config_reg = readl(&regs->confr);
config_reg |= GQSPI_STRT_GEN_FIFO;
@ -652,13 +647,8 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv,
}
}
debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
(unsigned long)buf, (unsigned long)priv->rx_buf,
*buf, actuallen);
if (!timeout) {
printf("IO timeout: %d\n", readl(&regs->isr));
return -1;
}
if (!timeout)
return log_msg_retz("Timeout\n", timeout);
}
return 0;
@ -695,26 +685,18 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
while (priv->len) {
zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
}
ret = wait_for_bit_le32(&dma_regs->dmaisr,
GQSPI_DMA_DST_I_STS_DONE, 1,
GQSPI_TIMEOUT, 1);
if (ret) {
printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
return -ETIMEDOUT;
}
if (ret)
return log_msg_ret("Timeout:\n", ret);
invalidate_dcache_range(addr, addr + size);
writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
(unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
actuallen);
if (buf != priv->rx_buf)
memcpy(priv->rx_buf, buf, actuallen);
@ -731,6 +713,8 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
u32 *buf;
u32 actuallen = priv->len;
log_debug("%s, length: %d\r\n", __func__, priv->len);
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK;

1
include/configs/mvebu_armada-37xx.h
View file

@ -30,7 +30,6 @@
/*
* Environment
*/
#define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */
#ifdef CONFIG_MMC
#define BOOT_TARGET_DEVICES_MMC(func, i) func(MMC, mmc, i)

14
include/dm/ofnode.h
View file

@ -976,13 +976,23 @@ const char *ofnode_read_chosen_string(const char *propname);
*/
ofnode ofnode_get_chosen_node(const char *propname);
/**
* ofnode_read_baud() - get the baudrate from string value of chosen property
*
* This looks for stdout-path property within the /chosen node and parses its
* value to return baudrate.
*
* This only works with the control FDT.
*
* Return: baudrate value if found, else -ve error code
*/
int ofnode_read_baud(void);
/**
* ofnode_read_aliases_prop() - get the value of a aliases property
*
* This looks for a property within the /aliases node and returns its value
*
* This only works with the control FDT.
*
* @propname: Property name to look for
* @sizep: Returns size of property, or `FDT_ERR_...` error code if function
* returns NULL

9
include/dt-bindings/net/mscc-phy-vsc8531.h
View file

@ -28,13 +28,4 @@
#define VSC8531_FORCE_LED_OFF 14
#define VSC8531_FORCE_LED_ON 15
#define VSC8531_RGMII_CLK_DELAY_0_2_NS 0
#define VSC8531_RGMII_CLK_DELAY_0_8_NS 1
#define VSC8531_RGMII_CLK_DELAY_1_1_NS 2
#define VSC8531_RGMII_CLK_DELAY_1_7_NS 3
#define VSC8531_RGMII_CLK_DELAY_2_0_NS 4
#define VSC8531_RGMII_CLK_DELAY_2_3_NS 5
#define VSC8531_RGMII_CLK_DELAY_2_6_NS 6
#define VSC8531_RGMII_CLK_DELAY_3_4_NS 7
#endif

8
include/env_default.h
View file

@ -21,7 +21,7 @@ env_t embedded_environment __UBOOT_ENV_SECTION__(environment) = {
{
#elif defined(DEFAULT_ENV_INSTANCE_STATIC)
static char default_environment[] = {
#elif defined(DEFAULT_ENV_IS_RW)
#elif defined(CONFIG_DEFAULT_ENV_IS_RW)
char default_environment[] = {
#else
const char default_environment[] = {
@ -42,7 +42,7 @@ const char default_environment[] = {
#if defined(CONFIG_BOOTDELAY)
"bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0"
#endif
#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
#if !defined(CONFIG_OF_SERIAL_BAUD) && defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
"baudrate=" __stringify(CONFIG_BAUDRATE) "\0"
#endif
#ifdef CONFIG_LOADS_ECHO
@ -118,6 +118,10 @@ const char default_environment[] = {
#endif
#ifdef CFG_EXTRA_ENV_SETTINGS
CFG_EXTRA_ENV_SETTINGS
#endif
#ifdef CONFIG_OF_SERIAL_BAUD
/* Padding for baudrate at the end when environment is writable */
"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
#endif
"\0"
#else /* CONFIG_USE_DEFAULT_ENV_FILE */

2
include/env_internal.h
View file

@ -89,7 +89,7 @@ typedef struct environment_s {
extern env_t embedded_environment;
#endif /* ENV_IS_EMBEDDED */
#ifdef DEFAULT_ENV_IS_RW
#ifdef CONFIG_DEFAULT_ENV_IS_RW
extern char default_environment[];
#else
extern const char default_environment[];

7
include/serial.h
View file

@ -339,6 +339,13 @@ int serial_setconfig(struct udevice *dev, uint config);
*/
int serial_getinfo(struct udevice *dev, struct serial_device_info *info);
/**
* fetch_baud_from_dtb() - Fetch the baudrate value from DT
*
* Return: baudrate if OK, -ve on error
*/
int fetch_baud_from_dtb(void);
void atmel_serial_initialize(void);
void mcf_serial_initialize(void);
void mpc85xx_serial_initialize(void);

1
test/dm/serial.c
View file

@ -29,6 +29,7 @@ static int dm_test_serial(struct unit_test_state *uts)
&dev_serial));
ut_assertok(serial_tstc());
ut_asserteq(115200, fetch_baud_from_dtb());
/*
* test with default config which is the only one supported by
* sandbox_serial driver