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arm: exynos: fix clock calculation

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There are differnce with clock calcuation by cpu variations.
This patch will fix it according to user manual.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
This commit is contained in:
Minkyu Kang 2013-07-05 19:08:33 +09:00
parent 9dfa3d0734
commit e161f60f4d
1 changed files with 38 additions and 5 deletions
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41
arch/arm/cpu/armv7/exynos/clock.c
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@ -27,6 +27,10 @@
#include <asm/arch/clk.h> #include <asm/arch/clk.h>
#include <asm/arch/periph.h> #include <asm/arch/periph.h>
#define PLL_DIV_1024 1024
#define PLL_DIV_65535 65535
#define PLL_DIV_65536 65536
/* * /* *
* This structure is to store the src bit, div bit and prediv bit * This structure is to store the src bit, div bit and prediv bit
* positions of the peripheral clocks of the src and div registers * positions of the peripheral clocks of the src and div registers
@ -85,6 +89,7 @@ static struct set_epll_con_val exynos5_epll_div[] = {
static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
{ {
unsigned long m, p, s = 0, mask, fout; unsigned long m, p, s = 0, mask, fout;
unsigned int div;
unsigned int freq; unsigned int freq;
/* /*
* APLL_CON: MIDV [25:16] * APLL_CON: MIDV [25:16]
@ -110,14 +115,42 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
if (pllreg == EPLL) { if (pllreg == EPLL) {
k = k & 0xffff; k = k & 0xffff;
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / 65536) * (freq / (p * (1 << s))); fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
} else if (pllreg == VPLL) { } else if (pllreg == VPLL) {
k = k & 0xfff; k = k & 0xfff;
/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / 1024) * (freq / (p * (1 << s))); /*
* Exynos4210
* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
*
* Exynos4412
* FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
*
* Exynos5250
* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
*/
if (proid_is_exynos4210())
div = PLL_DIV_1024;
else if (proid_is_exynos4412())
div = PLL_DIV_65535;
else if (proid_is_exynos5250())
div = PLL_DIV_65536;
else
return 0;
fout = (m + k / div) * (freq / (p * (1 << s)));
} else { } else {
/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */ /*
* Exynos4210
* FOUT = MDIV * FIN / (PDIV * 2^SDIV)
*
* Exynos4412 / Exynos5250
* FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
*/
if (proid_is_exynos4210())
fout = m * (freq / (p * (1 << s))); fout = m * (freq / (p * (1 << s)));
else
fout = m * (freq / (p * (1 << (s - 1))));
} }
return fout; return fout;