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ram: rk3399: update cap and ddrconfig for each channel after init
We need to store all the ram related cap/map info back to register for each channel after all the init has been done in case some of register was reset during the process. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang
parent
c399dca834
commit
e0f907efa5
1 changed files with 81 additions and 78 deletions
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@ -1488,6 +1488,84 @@ static void dram_all_config(struct dram_info *dram,
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clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
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}
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static void set_cap_relate_config(const struct chan_info *chan,
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struct rk3399_sdram_params *params,
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unsigned int channel)
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{
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u32 *denali_ctl = chan->pctl->denali_ctl;
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u32 tmp;
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struct rk3399_msch_timings *noc_timing;
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if (params->base.dramtype == LPDDR3) {
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tmp = (8 << params->ch[channel].cap_info.bw) /
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(8 << params->ch[channel].cap_info.dbw);
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/**
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* memdata_ratio
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* 1 -> 0, 2 -> 1, 4 -> 2
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*/
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clrsetbits_le32(&denali_ctl[197], 0x7,
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(tmp >> 1));
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clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
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(tmp >> 1) << 8);
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}
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noc_timing = ¶ms->ch[channel].noc_timings;
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/*
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* noc timing bw relate timing is 32 bit, and real bw is 16bit
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* actually noc reg is setting at function dram_all_config
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*/
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if (params->ch[channel].cap_info.bw == 16 &&
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noc_timing->ddrmode.b.mwrsize == 2) {
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if (noc_timing->ddrmode.b.burstsize)
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noc_timing->ddrmode.b.burstsize -= 1;
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noc_timing->ddrmode.b.mwrsize -= 1;
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noc_timing->ddrtimingc0.b.burstpenalty *= 2;
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noc_timing->ddrtimingc0.b.wrtomwr *= 2;
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}
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}
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static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)
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{
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unsigned int cs0_row = params->ch[channel].cap_info.cs0_row;
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unsigned int col = params->ch[channel].cap_info.col;
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unsigned int bw = params->ch[channel].cap_info.bw;
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u16 ddr_cfg_2_rbc[] = {
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/*
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* [6] highest bit col
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* [5:3] max row(14+n)
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* [2] insertion row
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* [1:0] col(9+n),col, data bus 32bit
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*
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* highbitcol, max_row, insertion_row, col
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*/
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((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
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((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
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((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
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((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
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((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
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((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
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((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
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((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
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};
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u32 i;
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col -= (bw == 2) ? 0 : 1;
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col -= 9;
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for (i = 0; i < 4; i++) {
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if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
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(cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
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break;
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}
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if (i >= 4)
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i = -EINVAL;
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return i;
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}
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#if !defined(CONFIG_RAM_RK3399_LPDDR4)
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static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
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struct rk3399_sdram_params *params)
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@ -1588,84 +1666,6 @@ static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)
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rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
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}
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static void set_cap_relate_config(const struct chan_info *chan,
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struct rk3399_sdram_params *params,
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unsigned int channel)
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{
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u32 *denali_ctl = chan->pctl->denali_ctl;
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u32 tmp;
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struct rk3399_msch_timings *noc_timing;
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if (params->base.dramtype == LPDDR3) {
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tmp = (8 << params->ch[channel].cap_info.bw) /
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(8 << params->ch[channel].cap_info.dbw);
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/**
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* memdata_ratio
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* 1 -> 0, 2 -> 1, 4 -> 2
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*/
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clrsetbits_le32(&denali_ctl[197], 0x7,
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(tmp >> 1));
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clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
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(tmp >> 1) << 8);
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}
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noc_timing = ¶ms->ch[channel].noc_timings;
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/*
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* noc timing bw relate timing is 32 bit, and real bw is 16bit
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* actually noc reg is setting at function dram_all_config
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*/
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if (params->ch[channel].cap_info.bw == 16 &&
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noc_timing->ddrmode.b.mwrsize == 2) {
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if (noc_timing->ddrmode.b.burstsize)
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noc_timing->ddrmode.b.burstsize -= 1;
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noc_timing->ddrmode.b.mwrsize -= 1;
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noc_timing->ddrtimingc0.b.burstpenalty *= 2;
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noc_timing->ddrtimingc0.b.wrtomwr *= 2;
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}
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}
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static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)
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{
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unsigned int cs0_row = params->ch[channel].cap_info.cs0_row;
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unsigned int col = params->ch[channel].cap_info.col;
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unsigned int bw = params->ch[channel].cap_info.bw;
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u16 ddr_cfg_2_rbc[] = {
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/*
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* [6] highest bit col
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* [5:3] max row(14+n)
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* [2] insertion row
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* [1:0] col(9+n),col, data bus 32bit
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*
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* highbitcol, max_row, insertion_row, col
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*/
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((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
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((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
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((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
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((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
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((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
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((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
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((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
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((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
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};
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u32 i;
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col -= (bw == 2) ? 0 : 1;
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col -= 9;
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for (i = 0; i < 4; i++) {
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if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
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(cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
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break;
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}
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if (i >= 4)
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i = -EINVAL;
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return i;
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}
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/**
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* read mr_num mode register
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* rank = 1: cs0
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@ -2592,8 +2592,11 @@ static int sdram_init(struct dram_info *dram,
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}
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sdram_print_ddr_info(cap_info, ¶ms->base);
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set_memory_map(chan, channel, params);
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cap_info->ddrconfig = calculate_ddrconfig(params, channel);
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set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
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set_cap_relate_config(chan, params, channel);
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}
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if (params->base.num_channels == 0) {
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