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https://github.com/u-boot/u-boot.git
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mtd: resync with Linux-3.7.1
This patch is essentially an update of u-boot MTD subsystem to the state of Linux-3.7.1 with exclusion of some bits: - the update is concentrated on NAND, no onenand or CFI/NOR/SPI flashes interfaces are updated EXCEPT for API changes. - new large NAND chips support is there, though some updates have got in Linux-3.8.-rc1, (which will follow on top of this patch). To produce this update I used tag v3.7.1 of linux-stable repository. The update was made using application of relevant patches, with changes relevant to U-Boot-only stuff sticked together to keep bisectability. Then all changes were grouped together to this patch. Signed-off-by: Sergey Lapin <slapin@ossfans.org> [scottwood@freescale.com: some eccstrength and build fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Sergey Lapin
Scott Wood
parent
a1b81ab26f
commit
dfe64e2c89
48 changed files with 2204 additions and 1702 deletions
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@ -46,7 +46,7 @@ extern void nand_wait_ready(struct mtd_info *mtd);
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* is supported now. If you add a chip with bigger oobsize/page
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* adjust this accordingly.
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*/
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#define NAND_MAX_OOBSIZE 576
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#define NAND_MAX_OOBSIZE 640
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#define NAND_MAX_PAGESIZE 8192
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/*
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@ -82,6 +82,8 @@ extern void nand_wait_ready(struct mtd_info *mtd);
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#define NAND_CMD_READID 0x90
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#define NAND_CMD_ERASE2 0xd0
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#define NAND_CMD_PARAM 0xec
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#define NAND_CMD_GET_FEATURES 0xee
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#define NAND_CMD_SET_FEATURES 0xef
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#define NAND_CMD_RESET 0xff
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#define NAND_CMD_LOCK 0x2a
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@ -142,7 +144,7 @@ typedef enum {
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#define NAND_ECC_READ 0
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/* Reset Hardware ECC for write */
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#define NAND_ECC_WRITE 1
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/* Enable Hardware ECC before syndrom is read back from flash */
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/* Enable Hardware ECC before syndrome is read back from flash */
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#define NAND_ECC_READSYN 2
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/* Bit mask for flags passed to do_nand_read_ecc */
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@ -153,9 +155,7 @@ typedef enum {
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* Option constants for bizarre disfunctionality and real
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* features.
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*/
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/* Chip can not auto increment pages */
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#define NAND_NO_AUTOINCR 0x00000001
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/* Buswitdh is 16 bit */
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/* Buswidth is 16 bit */
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#define NAND_BUSWIDTH_16 0x00000002
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/* Device supports partial programming without padding */
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#define NAND_NO_PADDING 0x00000004
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@ -179,12 +179,6 @@ typedef enum {
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* This happens with the Renesas AG-AND chips, possibly others.
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*/
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#define BBT_AUTO_REFRESH 0x00000080
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/*
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* Chip does not require ready check on read. true
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* for all large page devices, as they do not support
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* autoincrement.
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*/
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#define NAND_NO_READRDY 0x00000100
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/* Chip does not allow subpage writes */
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#define NAND_NO_SUBPAGE_WRITE 0x00000200
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@ -202,34 +196,21 @@ typedef enum {
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(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
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/* Macros to identify the above */
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#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
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#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
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#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
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#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
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#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
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/* Non chip related options */
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/*
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* Use a flash based bad block table. OOB identifier is saved in OOB area.
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* This option is passed to the default bad block table function.
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*/
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#define NAND_USE_FLASH_BBT 0x00010000
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/* This option skips the bbt scan during initialization. */
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#define NAND_SKIP_BBTSCAN 0x00020000
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#define NAND_SKIP_BBTSCAN 0x00010000
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/*
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* This option is defined if the board driver allocates its own buffers
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* (e.g. because it needs them DMA-coherent).
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*/
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#define NAND_OWN_BUFFERS 0x00040000
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#define NAND_OWN_BUFFERS 0x00020000
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/* Chip may not exist, so silence any errors in scan */
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#define NAND_SCAN_SILENT_NODEV 0x00080000
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/*
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* If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch
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* the OOB area.
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*/
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#define NAND_USE_FLASH_BBT_NO_OOB 0x00800000
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/* Create an empty BBT with no vendor information if the BBT is available */
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#define NAND_CREATE_EMPTY_BBT 0x01000000
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#define NAND_SCAN_SILENT_NODEV 0x00040000
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/* Options set by nand scan */
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/* bbt has already been read */
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@ -244,6 +225,21 @@ typedef enum {
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/* Keep gcc happy */
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struct nand_chip;
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/* ONFI timing mode, used in both asynchronous and synchronous mode */
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#define ONFI_TIMING_MODE_0 (1 << 0)
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#define ONFI_TIMING_MODE_1 (1 << 1)
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#define ONFI_TIMING_MODE_2 (1 << 2)
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#define ONFI_TIMING_MODE_3 (1 << 3)
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#define ONFI_TIMING_MODE_4 (1 << 4)
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#define ONFI_TIMING_MODE_5 (1 << 5)
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#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
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/* ONFI feature address */
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#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
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/* ONFI subfeature parameters length */
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#define ONFI_SUBFEATURE_PARAM_LEN 4
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struct nand_onfi_params {
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/* rev info and features block */
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/* 'O' 'N' 'F' 'I' */
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@ -326,27 +322,32 @@ struct nand_hw_control {
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};
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/**
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* struct nand_ecc_ctrl - Control structure for ecc
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* @mode: ecc mode
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* @steps: number of ecc steps per page
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* @size: data bytes per ecc step
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* @bytes: ecc bytes per step
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* @total: total number of ecc bytes per page
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* @prepad: padding information for syndrome based ecc generators
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* @postpad: padding information for syndrome based ecc generators
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* struct nand_ecc_ctrl - Control structure for ECC
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* @mode: ECC mode
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* @steps: number of ECC steps per page
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* @size: data bytes per ECC step
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* @bytes: ECC bytes per step
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* @strength: max number of correctible bits per ECC step
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* @total: total number of ECC bytes per page
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* @prepad: padding information for syndrome based ECC generators
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* @postpad: padding information for syndrome based ECC generators
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* @layout: ECC layout control struct pointer
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* @priv: pointer to private ecc control data
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* @hwctl: function to control hardware ecc generator. Must only
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* @priv: pointer to private ECC control data
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* @hwctl: function to control hardware ECC generator. Must only
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* be provided if an hardware ECC is available
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* @calculate: function for ecc calculation or readback from ecc hardware
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* @correct: function for ecc correction, matching to ecc generator (sw/hw)
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* @calculate: function for ECC calculation or readback from ECC hardware
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* @correct: function for ECC correction, matching to ECC generator (sw/hw)
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* @read_page_raw: function to read a raw page without ECC
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* @write_page_raw: function to write a raw page without ECC
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* @read_page: function to read a page according to the ecc generator
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* requirements.
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* @read_subpage: function to read parts of the page covered by ECC.
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* @write_page: function to write a page according to the ecc generator
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* @read_page: function to read a page according to the ECC generator
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* requirements; returns maximum number of bitflips corrected in
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* any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
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* @read_subpage: function to read parts of the page covered by ECC;
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* returns same as read_page()
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* @write_page: function to write a page according to the ECC generator
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* requirements.
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* @write_oob_raw: function to write chip OOB data without ECC
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* @read_oob_raw: function to read chip OOB data without ECC
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* @read_oob: function to read chip OOB data
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* @write_oob: function to write chip OOB data
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*/
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@ -356,6 +357,7 @@ struct nand_ecc_ctrl {
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int size;
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int bytes;
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int total;
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int strength;
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int prepad;
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int postpad;
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struct nand_ecclayout *layout;
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@ -366,25 +368,28 @@ struct nand_ecc_ctrl {
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int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
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uint8_t *calc_ecc);
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int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int page);
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void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf);
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uint8_t *buf, int oob_required, int page);
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int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf, int oob_required);
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int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int page);
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uint8_t *buf, int oob_required, int page);
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int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
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uint32_t offs, uint32_t len, uint8_t *buf);
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void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf);
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int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page,
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int sndcmd);
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int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf, int oob_required);
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int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
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int page);
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int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
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int page);
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int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
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int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
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int page);
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};
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/**
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* struct nand_buffers - buffer structure for read/write
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* @ecccalc: buffer for calculated ecc
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* @ecccode: buffer for ecc read from flash
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* @ecccalc: buffer for calculated ECC
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* @ecccode: buffer for ECC read from flash
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* @databuf: buffer for data - dynamically sized
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*
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* Do not change the order of buffers. databuf and oobrbuf must be in
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@ -418,7 +423,7 @@ struct nand_buffers {
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* mtd->oobsize, mtd->writesize and so on.
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* @id_data contains the 8 bytes values of NAND_CMD_READID.
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* Return with the bus width.
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* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing
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* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
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* device ready/busy line. If set to NULL no access to
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* ready/busy is available and the ready/busy information
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* is read from the chip status register.
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@ -426,17 +431,17 @@ struct nand_buffers {
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* commands to the chip.
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* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
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* ready.
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* @ecc: [BOARDSPECIFIC] ecc control ctructure
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* @ecc: [BOARDSPECIFIC] ECC control structure
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* @buffers: buffer structure for read/write
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* @hwcontrol: platform-specific hardware control structure
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* @ops: oob operation operands
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* @erase_cmd: [INTERN] erase command write function, selectable due
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* to AND support.
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* @scan_bbt: [REPLACEABLE] function to scan bad block table
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* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
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* data from array to read regs (tR).
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* @state: [INTERN] the current state of the NAND device
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* @oob_poi: poison value buffer
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* @oob_poi: "poison value buffer," used for laying out OOB data
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* before writing
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* @page_shift: [INTERN] number of address bits in a page (column
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* address bits).
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* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
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@ -445,10 +450,14 @@ struct nand_buffers {
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* @options: [BOARDSPECIFIC] various chip options. They can partly
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* be set to inform nand_scan about special functionality.
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* See the defines for further explanation.
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* @bbt_options: [INTERN] bad block specific options. All options used
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* here must come from bbm.h. By default, these options
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* will be copied to the appropriate nand_bbt_descr's.
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* @badblockpos: [INTERN] position of the bad block marker in the oob
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* area.
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* @badblockbits: [INTERN] number of bits to left-shift the bad block
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* number
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* @badblockbits: [INTERN] minimum number of set bits in a good block's
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* bad block marker position; i.e., BBM == 11110111b is
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* not bad when badblockbits == 7
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* @cellinfo: [INTERN] MLC/multichip data from chip ident
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* @numchips: [INTERN] number of physical chips
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* @chipsize: [INTERN] the size of one chip for multichip arrays
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@ -460,7 +469,9 @@ struct nand_buffers {
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* non 0 if ONFI supported.
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* @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
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* supported, 0 otherwise.
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* @ecclayout: [REPLACEABLE] the default ecc placement scheme
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* @onfi_set_features [REPLACEABLE] set the features for ONFI nand
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* @onfi_get_features [REPLACEABLE] get the features for ONFI nand
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* @ecclayout: [REPLACEABLE] the default ECC placement scheme
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* @bbt: [INTERN] bad block table pointer
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* @bbt_td: [REPLACEABLE] bad block table descriptor for flash
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* lookup.
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@ -468,9 +479,9 @@ struct nand_buffers {
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* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
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* bad block scan.
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* @controller: [REPLACEABLE] a pointer to a hardware controller
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* structure which is shared among multiple independend
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* structure which is shared among multiple independent
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* devices.
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* @priv: [OPTIONAL] pointer to private chip date
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* @priv: [OPTIONAL] pointer to private chip data
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* @errstat: [OPTIONAL] hardware specific function to perform
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* additional error status checks (determine if errors are
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* correctable).
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@ -501,10 +512,16 @@ struct nand_chip {
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int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
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int status, int page);
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int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf, int page, int cached, int raw);
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const uint8_t *buf, int oob_required, int page,
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int cached, int raw);
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int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
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int feature_addr, uint8_t *subfeature_para);
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int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
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int feature_addr, uint8_t *subfeature_para);
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int chip_delay;
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unsigned int options;
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unsigned int bbt_options;
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int page_shift;
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int phys_erase_shift;
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@ -534,8 +551,6 @@ struct nand_chip {
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struct nand_buffers *buffers;
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struct nand_hw_control hwcontrol;
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struct mtd_oob_ops ops;
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uint8_t *bbt;
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struct nand_bbt_descr *bbt_td;
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struct nand_bbt_descr *bbt_md;
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@ -557,6 +572,8 @@ struct nand_chip {
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#define NAND_MFR_HYNIX 0xad
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#define NAND_MFR_MICRON 0x2c
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#define NAND_MFR_AMD 0x01
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#define NAND_MFR_MACRONIX 0xc2
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#define NAND_MFR_EON 0x92
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/**
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* struct nand_flash_dev - NAND Flash Device ID Structure
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@ -615,9 +632,9 @@ extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
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* @partitions: mtd partition list
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* @chip_delay: R/B delay value in us
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* @options: Option flags, e.g. 16bit buswidth
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* @ecclayout: ecc layout info structure
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* @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
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* @ecclayout: ECC layout info structure
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* @part_probe_types: NULL-terminated array of probe types
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* @priv: hardware controller specific settings
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*/
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struct platform_nand_chip {
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int nr_chips;
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@ -627,8 +644,8 @@ struct platform_nand_chip {
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struct nand_ecclayout *ecclayout;
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int chip_delay;
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unsigned int options;
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unsigned int bbt_options;
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const char **part_probe_types;
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void *priv;
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};
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/* Keep gcc happy */
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@ -650,6 +667,7 @@ struct platform_nand_ctrl {
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int (*dev_ready)(struct mtd_info *mtd);
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void (*select_chip)(struct mtd_info *mtd, int chip);
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void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
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unsigned char (*read_byte)(struct mtd_info *mtd);
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void *priv;
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};
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@ -679,4 +697,23 @@ void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
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void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
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uint8_t nand_read_byte(struct mtd_info *mtd);
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/* return the supported asynchronous timing mode. */
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#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
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static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
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{
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if (!chip->onfi_version)
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return ONFI_TIMING_MODE_UNKNOWN;
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return le16_to_cpu(chip->onfi_params.async_timing_mode);
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}
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/* return the supported synchronous timing mode. */
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static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
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{
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if (!chip->onfi_version)
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return ONFI_TIMING_MODE_UNKNOWN;
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return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
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}
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#endif
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#endif /* __LINUX_MTD_NAND_H */
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