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xtensa: add support for the xtensa processor architecture [1/2]

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The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Cadence.

This is the first part of the basic architecture port with changes to
common files. The 'arch/xtensa' directory, and boards and additional
drivers will be in separate commits.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Chris Zankel 2016-08-10 18:36:43 +03:00 • committed by Tom Rini
parent f225d39d30
commit de5e5cea02
9 changed files with 179 additions and 6 deletions
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4
include/linux/stat.h
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@ -126,7 +126,7 @@ struct stat {
#endif /* __MIPS__ */
#if defined(__AVR32__) || defined(__SH__)
#if defined(__AVR32__) || defined(__SH__) || defined(__XTENSA__)
struct stat {
unsigned long st_dev;
@ -149,7 +149,7 @@ struct stat {
unsigned long __unused5;
};
#endif /* __AVR32__ || __SH__ */
#endif /* __AVR32__ || __SH__ || __XTENSA__ */
#ifdef __cplusplus
}