Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-05-09 03:21:51 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Make DDR interleaving mode work correctly

Browse source 
Fix some bugs:
  1. Correctly set intlv_ctl in cs_config.
  2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
  3. Set base_address and total memory for each ddr controller in memory
     controller interleaving mode.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
This commit is contained in:
Haiying Wang 2008-10-03 12:36:39 -04:00 • committed by Wolfgang Denk
parent 1c9aa76bf9
commit dbbbb3abef
3 changed files with 66 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

5
cpu/mpc8xxx/ddr/main.c
View file

@ -179,6 +179,7 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
if (*memctl_interleaving) {
phys_addr_t addr;
phys_size_t total_mem_per_ctlr = 0;
/*
* If interleaving between memory controllers,
@ -197,14 +198,18 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
addr = 0;
pinfo->common_timing_params[i].base_address =
(phys_addr_t)addr;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
unsigned long long cap
= pinfo->dimm_params[i][j].capacity;
pinfo->dimm_params[i][j].base_address = addr;
addr += (phys_addr_t)(cap >> dbw_cap_adj[i]);
total_mem_per_ctlr += cap >> dbw_cap_adj[i];
}
}
pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
} else {
/*
* Simple linear assignment if memory