Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-05-08 10:39:08 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

arm: socfpga: Convert system manager from struct to defines

Browse source 
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get system manager base address from DT node instead of
using #define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This commit is contained in:
Ley Foon Tan 2019-11-08 10:38:20 +08:00 • committed by Marek Vasut
parent bb25aca134
commit db5741f7a8
25 changed files with 267 additions and 422 deletions
Download patch file Download diff file Expand all files Collapse all files

12
drivers/ddr/altera/sdram_gen5.c
View file

@ -40,9 +40,6 @@ struct sdram_prot_rule {
u32 hi_prot_id;
};
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
/**
@ -455,12 +452,14 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
int ret;
writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
writel(rows,
socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
sdr_load_regs(sdr_ctrl, cfg);
/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
writel(cfg->fpgaport_rst,
socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(3));
/* only enable if the FPGA is programmed */
if (fpgamgr_test_fpga_ready()) {
@ -516,7 +515,8 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
* since the FB specifies we modify ROWBITs to work around SDRAM
* controller issue.
*/
row = readl(&sysmgr_regs->iswgrp_handoff[4]);
row = readl(socfpga_get_sysmgr_addr() +
SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
if (row == 0)
row = rowbits;
/*

6
drivers/ddr/altera/sdram_s10.c
View file

@ -33,9 +33,6 @@ struct altera_sdram_platdata {
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_system_manager *sysmgr_regs =
(void *)SOCFPGA_SYSMGR_ADDRESS;
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
#define PGTABLE_OFF 0x4000
@ -151,7 +148,8 @@ static int emif_reset(struct altera_sdram_platdata *plat)
static int poll_hmc_clock_status(void)
{
return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
SYSMGR_S10_HMC_CLK),
SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
}