Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-05-08 19:11:53 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

New for 2020.04

Browse source 
---------------
 
 - New boards
 	Embedded Artists COM board
 	Xea Board
 - Switch to DM:
 	Aristainetos boards
 	Toradex colibri (DM_ETH)
 	iCubox
 	GE bx50v3
 	mx7dsabre (DM_ETH)
 	cx9020
 - New features:
 	Bootaux with elf files
 	Default SYS_THUMB_BUILD for i.MX6/7
 - Fixes:
 	DHCOM i.MX6 PDK
 	Engicam
 	i.MX8M tools (imx8m_image)
 
 Travis: 633679664
 -----BEGIN PGP SIGNATURE-----
 
 iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAl4UhxIPHHNiYWJpY0Bk
 ZW54LmRlAAoJECjE2NMq1et3MZYMAMEttt0cNxBg0/zBjNuMSn3Bq1lpN+KKsY97
 Cme06wZQdlbdfHhXyKiVfky2vjrZa1nacUgqSQlJdzvsPQbg9TE/8zxTd13BNw6C
 Tn6IHS7godvz9Puf0HD8skoYBpVm/LQKmSEfcPAEGOSnHzZx/MrMU0Qze3PgqWu5
 0xbp8yBsyVw96/zBRZtbwXy4COuS1viFrbf82EgHAZUsmXpgvJB59i8rOewwWNR1
 TpyhPbHlq42X+0Qrwq0RGtUr+t4tI6czlxeReOBgb1/YqJGJ6rEqbGm90XROW3sA
 IeU5PY7LUk8OFRQtyfBSSYgFgFmgOYzfpXe9YSUoIxV55OvCad7ksaRctjPJnKqy
 CndINrG9JnV9T5N0LczAgVFXWT49ybPziyZRDHERDg1XosuHnNk7r0co05uacYUN
 ZFgB21mzQ8qGPAd1C3tMXG05ZA9cdRCmWxKxxF6z2/2FT15euZQ0obwAR1HsiJmZ
 wLbyPl1Hi7ZkwvTT/Wk3se0zGpNj2A==
 =vOZ+
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20200107' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

New for 2020.04
---------------

- New boards
	Embedded Artists COM board
	Xea Board
- Switch to DM:
	Aristainetos boards
	Toradex colibri (DM_ETH)
	iCubox
	GE bx50v3
	mx7dsabre (DM_ETH)
	cx9020
- New features:
	Bootaux with elf files
	Default SYS_THUMB_BUILD for i.MX6/7
- Fixes:
	DHCOM i.MX6 PDK
	Engicam
	i.MX8M tools (imx8m_image)

Travis: 633679664
This commit is contained in:
Tom Rini 2020-01-07 08:45:43 -05:00
commit d8a3f5259a
207 changed files with 13950 additions and 3277 deletions
Download patch file Download diff file Expand all files Collapse all files

11
drivers/ddr/imx/imx8m/ddr_init.c
View file

@ -20,9 +20,10 @@ void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
}
}
void ddr_init(struct dram_timing_info *dram_timing)
int ddr_init(struct dram_timing_info *dram_timing)
{
unsigned int tmp, initial_drate, target_freq;
int ret;
debug("DDRINFO: start DRAM init\n");
@ -98,7 +99,11 @@ void ddr_init(struct dram_timing_info *dram_timing)
* accessing relevant PUB registers
*/
debug("DDRINFO:ddrphy config start\n");
ddr_cfg_phy(dram_timing);
ret = ddr_cfg_phy(dram_timing);
if (ret)
return ret;
debug("DDRINFO: ddrphy config done\n");
/*
@ -165,4 +170,6 @@ void ddr_init(struct dram_timing_info *dram_timing)
/* save the dram timing config into memory */
dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
return 0;
}

9
drivers/ddr/imx/imx8m/ddrphy_train.c
View file

@ -8,13 +8,14 @@
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
void ddr_cfg_phy(struct dram_timing_info *dram_timing)
int ddr_cfg_phy(struct dram_timing_info *dram_timing)
{
struct dram_cfg_param *dram_cfg;
struct dram_fsp_msg *fsp_msg;
unsigned int num;
int i = 0;
int j = 0;
int ret;
/* initialize PHY configuration */
dram_cfg = dram_timing->ddrphy_cfg;
@ -60,7 +61,9 @@ void ddr_cfg_phy(struct dram_timing_info *dram_timing)
dwc_ddrphy_apb_wr(0xd0099, 0x0);
/* Wait for the training firmware to complete */
wait_ddrphy_training_complete();
ret = wait_ddrphy_training_complete();
if (ret)
return ret;
/* Halt the microcontroller. */
dwc_ddrphy_apb_wr(0xd0099, 0x1);
@ -83,4 +86,6 @@ void ddr_cfg_phy(struct dram_timing_info *dram_timing)
/* save the ddr PHY trained CSR in memory for low power use */
ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num);
return 0;
}

8
drivers/ddr/imx/imx8m/ddrphy_utils.c
View file

@ -84,7 +84,7 @@ static inline void decode_streaming_message(void)
debug("\n");
}
void wait_ddrphy_training_complete(void)
int wait_ddrphy_training_complete(void)
{
unsigned int mail;
@ -95,10 +95,10 @@ void wait_ddrphy_training_complete(void)
decode_streaming_message();
} else if (mail == 0x07) {
debug("Training PASS\n");
break;
return 0;
} else if (mail == 0xff) {
printf("Training FAILED\n");
break;
debug("Training FAILED\n");
return -1;
}
}
}