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clk: ti: clk-k3-pll: Change variable name reg to base

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base is more appropriate for the usage as the variable stores the base
address and seems more accurate w.r.t reg. Change reg to base.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
This commit is contained in:
Manorit Chawdhry 2024-11-21 17:32:52 +05:30 • committed by Tom Rini
parent 5d1aac358f
commit d6cd643c4e
1 changed files with 28 additions and 28 deletions
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56
drivers/clk/ti/clk-k3-pll.c
View file

@ -75,7 +75,7 @@
*/
struct ti_pll_clk {
struct clk clk;
void __iomem *reg;
void __iomem *base;
};
#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk)
@ -93,7 +93,7 @@ static int ti_pll_wait_for_lock(struct clk *clk)
int success;
for (i = 0; i < 100000; i++) {
stat = readl(pll->reg + PLL_16FFT_STAT);
stat = readl(pll->base + PLL_16FFT_STAT);
if (stat & PLL_16FFT_STAT_LOCK) {
success = 1;
break;
@ -101,14 +101,14 @@ static int ti_pll_wait_for_lock(struct clk *clk)
}
/* Enable calibration if not in fractional mode of the FRACF PLL */
freq_ctrl1 = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
freq_ctrl1 = readl(pll->base + PLL_16FFT_FREQ_CTRL1);
pllfm = freq_ctrl1 & PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK;
pllfm >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT;
cfg = readl(pll->reg + PLL_16FFT_CFG);
cfg = readl(pll->base + PLL_16FFT_CFG);
pll_type = (cfg & PLL_16FFT_CFG_PLL_TYPE_MASK) >> PLL_16FFT_CFG_PLL_TYPE_SHIFT;
if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF && pllfm == 0) {
cal = readl(pll->reg + PLL_16FFT_CAL_CTRL);
cal = readl(pll->base + PLL_16FFT_CAL_CTRL);
/* Enable calibration for FRACF */
cal |= PLL_16FFT_CAL_CTRL_CAL_EN;
@ -124,11 +124,11 @@ static int ti_pll_wait_for_lock(struct clk *clk)
cal |= 2 << PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT;
/* Note this register does not readback the written value. */
writel(cal, pll->reg + PLL_16FFT_CAL_CTRL);
writel(cal, pll->base + PLL_16FFT_CAL_CTRL);
success = 0;
for (i = 0; i < 100000; i++) {
stat = readl(pll->reg + PLL_16FFT_CAL_STAT);
stat = readl(pll->base + PLL_16FFT_CAL_STAT);
if (stat & PLL_16FFT_CAL_STAT_CAL_LOCK) {
success = 1;
break;
@ -156,14 +156,14 @@ static ulong ti_pll_clk_get_rate(struct clk *clk)
u32 ctrl;
/* Check if we are in bypass */
ctrl = readl(pll->reg + PLL_16FFT_CTRL);
ctrl = readl(pll->base + PLL_16FFT_CTRL);
if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
return parent_freq;
pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
pllm = readl(pll->base + PLL_16FFT_FREQ_CTRL0);
pllfm = readl(pll->base + PLL_16FFT_FREQ_CTRL1);
plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
plld = readl(pll->base + PLL_16FFT_DIV_CTRL) &
PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
current_freq = parent_freq * pllm / plld;
@ -213,9 +213,9 @@ static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
}
/* Put PLL to bypass mode */
ctrl = readl(pll->reg + PLL_16FFT_CTRL);
ctrl = readl(pll->base + PLL_16FFT_CTRL);
ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
writel(ctrl, pll->reg + PLL_16FFT_CTRL);
writel(ctrl, pll->base + PLL_16FFT_CTRL);
if (rate == parent_freq) {
debug("%s: put %s to bypass\n", __func__, clk->dev->name);
@ -242,21 +242,21 @@ static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
else
ctrl &= ~PLL_16FFT_CTRL_DSM_EN;
writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0);
writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1);
writel(pllm, pll->base + PLL_16FFT_FREQ_CTRL0);
writel(pllfm, pll->base + PLL_16FFT_FREQ_CTRL1);
/*
* div_ctrl register contains other divider values, so rmw
* only plld and leave existing values alone
*/
div_ctrl = readl(pll->reg + PLL_16FFT_DIV_CTRL);
div_ctrl = readl(pll->base + PLL_16FFT_DIV_CTRL);
div_ctrl &= ~PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
div_ctrl |= plld;
writel(div_ctrl, pll->reg + PLL_16FFT_DIV_CTRL);
writel(div_ctrl, pll->base + PLL_16FFT_DIV_CTRL);
ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
ctrl |= PLL_16FFT_CTRL_PLL_EN;
writel(ctrl, pll->reg + PLL_16FFT_CTRL);
writel(ctrl, pll->base + PLL_16FFT_CTRL);
ret = ti_pll_wait_for_lock(clk);
if (ret)
@ -284,10 +284,10 @@ static int ti_pll_clk_enable(struct clk *clk)
struct ti_pll_clk *pll = to_clk_pll(clk);
u32 ctrl;
ctrl = readl(pll->reg + PLL_16FFT_CTRL);
ctrl = readl(pll->base + PLL_16FFT_CTRL);
ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
ctrl |= PLL_16FFT_CTRL_PLL_EN;
writel(ctrl, pll->reg + PLL_16FFT_CTRL);
writel(ctrl, pll->base + PLL_16FFT_CTRL);
return ti_pll_wait_for_lock(clk);
}
@ -297,9 +297,9 @@ static int ti_pll_clk_disable(struct clk *clk)
struct ti_pll_clk *pll = to_clk_pll(clk);
u32 ctrl;
ctrl = readl(pll->reg + PLL_16FFT_CTRL);
ctrl = readl(pll->base + PLL_16FFT_CTRL);
ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
writel(ctrl, pll->reg + PLL_16FFT_CTRL);
writel(ctrl, pll->base + PLL_16FFT_CTRL);
return 0;
}
@ -323,7 +323,7 @@ struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
if (!pll)
return ERR_PTR(-ENOMEM);
pll->reg = reg;
pll->base = reg;
ret = clk_register(&pll->clk, "ti-pll-clk", name, parent_name);
if (ret) {
@ -333,19 +333,19 @@ struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
}
/* Unlock the PLL registers */
writel(PLL_KICK0_VALUE, pll->reg + PLL_KICK0);
writel(PLL_KICK1_VALUE, pll->reg + PLL_KICK1);
writel(PLL_KICK0_VALUE, pll->base + PLL_KICK0);
writel(PLL_KICK1_VALUE, pll->base + PLL_KICK1);
/* Enable all HSDIV outputs */
cfg = readl(pll->reg + PLL_16FFT_CFG);
cfg = readl(pll->base + PLL_16FFT_CFG);
for (i = 0; i < 16; i++) {
hsdiv_presence_bit = BIT(16 + i);
hsdiv_ctrl_offs = 0x80 + (i * 4);
/* Enable HSDIV output if present */
if ((hsdiv_presence_bit & cfg) != 0UL) {
ctrl = readl(pll->reg + hsdiv_ctrl_offs);
ctrl = readl(pll->base + hsdiv_ctrl_offs);
ctrl |= PLL_16FFT_HSDIV_CTRL_CLKOUT_EN;
writel(ctrl, pll->reg + hsdiv_ctrl_offs);
writel(ctrl, pll->base + hsdiv_ctrl_offs);
}
}