mirror of
https://github.com/u-boot/u-boot.git
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Subtree merge tag 'v6.14-dts' of dts repo [1] into dts/upstream
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
This commit is contained in:
Tom Rini
commit
d6cc404b5f
842 changed files with 71735 additions and 6700 deletions
|
|
@ -1,25 +0,0 @@
|
|||
Altera SOCFPGA System Manager
|
||||
|
||||
Required properties:
|
||||
- compatible : "altr,sys-mgr"
|
||||
- reg : Should contain 1 register ranges(address and length)
|
||||
- cpu1-start-addr : CPU1 start address in hex.
|
||||
|
||||
Example:
|
||||
sysmgr@ffd08000 {
|
||||
compatible = "altr,sys-mgr";
|
||||
reg = <0xffd08000 0x1000>;
|
||||
cpu1-start-addr = <0xffd080c4>;
|
||||
};
|
||||
|
||||
ARM64 - Stratix10
|
||||
Required properties:
|
||||
- compatible : "altr,sys-mgr-s10"
|
||||
- reg : Should contain 1 register range(address and length)
|
||||
for system manager register.
|
||||
|
||||
Example:
|
||||
sysmgr@ffd12000 {
|
||||
compatible = "altr,sys-mgr-s10";
|
||||
reg = <0xffd12000 0x228>;
|
||||
};
|
||||
|
|
@ -38,6 +38,12 @@ properties:
|
|||
enum:
|
||||
- arm,coresight-dummy-source
|
||||
|
||||
arm,static-trace-id:
|
||||
description: If dummy source needs static id support, use this to set trace id.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
maximum: 111
|
||||
|
||||
out-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
|
|
|
|||
|
|
@ -45,7 +45,22 @@ properties:
|
|||
patternProperties:
|
||||
'^port@[01]$':
|
||||
description: Output connections to CoreSight Trace bus
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/graph.yaml#/$defs/endpoint-base
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
filter-source:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle to the coresight trace source device matching the
|
||||
hard coded filtering for this port
|
||||
|
||||
remote-endpoint: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
@ -72,6 +87,7 @@ examples:
|
|||
reg = <0>;
|
||||
replicator_out_port0: endpoint {
|
||||
remote-endpoint = <&etb_in_port>;
|
||||
filter-source = <&tpdm_video>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -79,6 +95,7 @@ examples:
|
|||
reg = <1>;
|
||||
replicator_out_port1: endpoint {
|
||||
remote-endpoint = <&tpiu_in_port>;
|
||||
filter-source = <&tpdm_mdss>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ description: |
|
|||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^ete([0-9a-f]+)$"
|
||||
pattern: "^ete(-[0-9]+)?$"
|
||||
compatible:
|
||||
items:
|
||||
- const: arm,embedded-trace-extension
|
||||
|
|
@ -55,13 +55,13 @@ examples:
|
|||
|
||||
# An ETE node without legacy CoreSight connections
|
||||
- |
|
||||
ete0 {
|
||||
ete-0 {
|
||||
compatible = "arm,embedded-trace-extension";
|
||||
cpu = <&cpu_0>;
|
||||
};
|
||||
# An ETE node with legacy CoreSight connections
|
||||
- |
|
||||
ete1 {
|
||||
ete-1 {
|
||||
compatible = "arm,embedded-trace-extension";
|
||||
cpu = <&cpu_1>;
|
||||
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@ properties:
|
|||
- description: AST2600 based boards
|
||||
items:
|
||||
- enum:
|
||||
- ampere,mtjefferson-bmc
|
||||
- ampere,mtmitchell-bmc
|
||||
- aspeed,ast2600-evb
|
||||
- aspeed,ast2600-evb-a1
|
||||
|
|
@ -91,6 +92,7 @@ properties:
|
|||
- ibm,everest-bmc
|
||||
- ibm,fuji-bmc
|
||||
- ibm,rainier-bmc
|
||||
- ibm,sbp1-bmc
|
||||
- ibm,system1-bmc
|
||||
- ibm,tacoma-bmc
|
||||
- inventec,starscream-bmc
|
||||
|
|
|
|||
|
|
@ -180,6 +180,13 @@ properties:
|
|||
- const: atmel,sama5d4
|
||||
- const: atmel,sama5
|
||||
|
||||
- description: Microchip SAMA7D65 Curiosity Board
|
||||
items:
|
||||
- const: microchip,sama7d65-curiosity
|
||||
- const: microchip,sama7d65
|
||||
- const: microchip,sama7d6
|
||||
- const: microchip,sama7
|
||||
|
||||
- items:
|
||||
- const: microchip,sama7g5ek # SAMA7G5 Evaluation Kit
|
||||
- const: microchip,sama7g5
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ PIT Timer required properties:
|
|||
PIT64B Timer required properties:
|
||||
- compatible: Should be "microchip,sam9x60-pit64b" or
|
||||
"microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
|
||||
"microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"
|
||||
- reg: Should contain registers location and length
|
||||
- interrupts: Should contain interrupt for PIT64B timer
|
||||
- clocks: Should contain the available clock sources for PIT64B timer.
|
||||
|
|
@ -27,12 +28,13 @@ Its subnodes can be:
|
|||
- watchdog: compatible should be "atmel,at91rm9200-wdt"
|
||||
|
||||
RAMC SDRAM/DDR Controller required properties:
|
||||
- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
|
||||
"atmel,at91sam9260-sdramc",
|
||||
"atmel,at91sam9g45-ddramc",
|
||||
"atmel,sama5d3-ddramc",
|
||||
"microchip,sam9x60-ddramc",
|
||||
"microchip,sama7g5-uddrc",
|
||||
- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" or
|
||||
"atmel,at91sam9260-sdramc" or
|
||||
"atmel,at91sam9g45-ddramc" or
|
||||
"atmel,sama5d3-ddramc" or
|
||||
"microchip,sam9x60-ddramc" or
|
||||
"microchip,sama7g5-uddrc" or
|
||||
"microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc" or
|
||||
"microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ properties:
|
|||
- enum:
|
||||
- netgear,r8000p
|
||||
- tplink,archer-c2300-v1
|
||||
- zyxel,ex3510b
|
||||
- const: brcm,bcm4906
|
||||
- const: brcm,bcm4908
|
||||
- const: brcm,bcmbca
|
||||
|
|
@ -115,6 +116,7 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- brcm,bcm96846
|
||||
- genexis,xg6846b
|
||||
- const: brcm,bcm6846
|
||||
- const: brcm,bcmbca
|
||||
|
||||
|
|
|
|||
40
dts/upstream/Bindings/arm/blaize.yaml
Normal file
40
dts/upstream/Bindings/arm/blaize.yaml
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/blaize.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Blaize Platforms
|
||||
|
||||
maintainers:
|
||||
- James Cowgill <james.cowgill@blaize.com>
|
||||
- Matt Redfearn <matt.redfearn@blaize.com>
|
||||
- Neil Jones <neil.jones@blaize.com>
|
||||
- Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
|
||||
|
||||
description: |
|
||||
Blaize Platforms using SoCs designed by Blaize Inc.
|
||||
|
||||
The products based on the BLZP1600 SoC:
|
||||
|
||||
- BLZP1600-SoM: SoM (System on Module)
|
||||
- BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM
|
||||
|
||||
BLZP1600 SoC integrates a dual core ARM Cortex A53 cluster
|
||||
and a Blaize Graph Streaming Processor for AI and ML workloads,
|
||||
plus a suite of connectivity and other peripherals.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Blaize BLZP1600 based boards
|
||||
items:
|
||||
- enum:
|
||||
- blaize,blzp1600-cb2
|
||||
- const: blaize,blzp1600
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
|
@ -1091,6 +1091,7 @@ properties:
|
|||
- dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
|
||||
- emcraft,imx8mp-navqp # i.MX8MP Emcraft Systems NavQ+ Kit
|
||||
- fsl,imx8mp-evk # i.MX8MP EVK Board
|
||||
- fsl,imx8mp-evk-revb4 # i.MX8MP EVK Rev B4 Board
|
||||
- gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
|
||||
|
|
@ -1106,6 +1107,15 @@ properties:
|
|||
- ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: ABB Boards with i.MX8M Plus Modules from ADLink
|
||||
items:
|
||||
- enum:
|
||||
- abb,imx8mp-aristanetos3-adpismarc # i.MX8MP ABB SoM on PI SMARC Board
|
||||
- abb,imx8mp-aristanetos3-helios # i.MX8MP ABB SoM on helios Board
|
||||
- abb,imx8mp-aristanetos3-proton2s # i.MX8MP ABB SoM on proton2s Board
|
||||
- const: abb,imx8mp-aristanetos3-som # i.MX8MP ABB SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Avnet (MSC Branded) Boards with SM2S i.MX8M Plus Modules
|
||||
items:
|
||||
- const: avnet,sm2s-imx8mp-14N0600E-ep1 # SM2S-IMX8PLUS-14N0600E on SM2-MB-EP1 Carrier Board
|
||||
|
|
@ -1262,6 +1272,7 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- fsl,imx8qm-mek # i.MX8QM MEK Board
|
||||
- fsl,imx8qm-mek-revd # i.MX8QM MEK Rev D Board
|
||||
- toradex,apalis-imx8 # Apalis iMX8 Modules
|
||||
- toradex,apalis-imx8-v1.1 # Apalis iMX8 V1.1 Modules
|
||||
- const: fsl,imx8qm
|
||||
|
|
@ -1290,6 +1301,7 @@ properties:
|
|||
- enum:
|
||||
- einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board
|
||||
- fsl,imx8qxp-mek # i.MX8QXP MEK Board
|
||||
- fsl,imx8qxp-mek-wcpu # i.MX8QXP MEK WCPU Board
|
||||
- const: fsl,imx8qxp
|
||||
|
||||
- description: i.MX8DXL based Boards
|
||||
|
|
|
|||
|
|
@ -239,6 +239,34 @@ properties:
|
|||
- enum:
|
||||
- mediatek,mt8183-pumpkin
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Chinchou (Asus Chromebook CZ1104CM2A/CZ1204CM2A)
|
||||
items:
|
||||
- const: google,chinchou-sku0
|
||||
- const: google,chinchou-sku2
|
||||
- const: google,chinchou-sku4
|
||||
- const: google,chinchou-sku5
|
||||
- const: google,chinchou
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Chinchou (Asus Chromebook CZ1104FM2A/CZ1204FM2A/CZ1104CM2A/CZ1204CM2A)
|
||||
items:
|
||||
- const: google,chinchou-sku1
|
||||
- const: google,chinchou-sku3
|
||||
- const: google,chinchou-sku6
|
||||
- const: google,chinchou-sku7
|
||||
- const: google,chinchou-sku17
|
||||
- const: google,chinchou-sku20
|
||||
- const: google,chinchou-sku22
|
||||
- const: google,chinchou-sku23
|
||||
- const: google,chinchou
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Chinchou360 (Asus Chromebook CZ1104FM2A/CZ1204FM2A Flip)
|
||||
items:
|
||||
- const: google,chinchou-sku16
|
||||
- const: google,chinchou-sku18
|
||||
- const: google,chinchou-sku19
|
||||
- const: google,chinchou-sku21
|
||||
- const: google,chinchou
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
|
||||
items:
|
||||
- const: google,steelix-sku393219
|
||||
|
|
@ -263,6 +291,19 @@ properties:
|
|||
- const: google,steelix-sku196608
|
||||
- const: google,steelix
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Starmie (ASUS Chromebook Enterprise CM30 (CM3001))
|
||||
items:
|
||||
- const: google,starmie-sku0
|
||||
- const: google,starmie-sku2
|
||||
- const: google,starmie-sku3
|
||||
- const: google,starmie
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Starmie (ASUS Chromebook Enterprise CM30 (CM3001))
|
||||
items:
|
||||
- const: google,starmie-sku1
|
||||
- const: google,starmie-sku4
|
||||
- const: google,starmie
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Steelix (Lenovo 300e Yoga Chromebook Gen 4)
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -307,6 +348,19 @@ properties:
|
|||
- enum:
|
||||
- mediatek,mt8186-evb
|
||||
- const: mediatek,mt8186
|
||||
- description: Google Ciri (Lenovo Chromebook Duet (11", 9))
|
||||
items:
|
||||
- enum:
|
||||
- google,ciri-sku0
|
||||
- google,ciri-sku1
|
||||
- google,ciri-sku2
|
||||
- google,ciri-sku3
|
||||
- google,ciri-sku4
|
||||
- google,ciri-sku5
|
||||
- google,ciri-sku6
|
||||
- google,ciri-sku7
|
||||
- const: google,ciri
|
||||
- const: mediatek,mt8188
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-evb
|
||||
|
|
@ -316,12 +370,6 @@ properties:
|
|||
- const: google,hayato-rev1
|
||||
- const: google,hayato
|
||||
- const: mediatek,mt8192
|
||||
- description: Google Hayato rev5
|
||||
items:
|
||||
- const: google,hayato-rev5-sku2
|
||||
- const: google,hayato-sku2
|
||||
- const: google,hayato
|
||||
- const: mediatek,mt8192
|
||||
- description: Google Spherion (Acer Chromebook 514)
|
||||
items:
|
||||
- const: google,spherion-rev3
|
||||
|
|
@ -330,11 +378,6 @@ properties:
|
|||
- const: google,spherion-rev0
|
||||
- const: google,spherion
|
||||
- const: mediatek,mt8192
|
||||
- description: Google Spherion rev4 (Acer Chromebook 514)
|
||||
items:
|
||||
- const: google,spherion-rev4
|
||||
- const: google,spherion
|
||||
- const: mediatek,mt8192
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8192-evb
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ description: |
|
|||
select:
|
||||
properties:
|
||||
compatible:
|
||||
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
|
||||
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
|
||||
required:
|
||||
- compatible
|
||||
|
||||
|
|
@ -31,7 +31,8 @@ properties:
|
|||
compatible:
|
||||
oneOf:
|
||||
# Preferred naming style for compatibles of SoC components:
|
||||
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
|
||||
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$"
|
||||
- pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
|
||||
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
|
||||
|
||||
# Legacy namings - variations of existing patterns/compatibles are OK,
|
||||
|
|
@ -39,9 +40,9 @@ properties:
|
|||
- pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
|
||||
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
|
||||
- pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
|
||||
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
|
||||
- enum:
|
||||
- qcom,dsi-ctrl-6g-qcm2290
|
||||
- qcom,gpucc-sdm630
|
||||
|
|
|
|||
|
|
@ -19,29 +19,42 @@ description: |
|
|||
|
||||
apq8016
|
||||
apq8026
|
||||
apq8064
|
||||
apq8074
|
||||
apq8084
|
||||
apq8094
|
||||
apq8096
|
||||
ipq4018
|
||||
ipq4019
|
||||
ipq5018
|
||||
ipq5332
|
||||
ipq5424
|
||||
ipq6018
|
||||
ipq8064
|
||||
ipq8074
|
||||
ipq9574
|
||||
mdm9615
|
||||
msm8226
|
||||
msm8660
|
||||
msm8916
|
||||
msm8917
|
||||
msm8926
|
||||
msm8929
|
||||
msm8939
|
||||
msm8953
|
||||
msm8956
|
||||
msm8960
|
||||
msm8974
|
||||
msm8974pro
|
||||
msm8976
|
||||
msm8992
|
||||
msm8994
|
||||
msm8996
|
||||
msm8996pro
|
||||
msm8998
|
||||
qcs404
|
||||
qcs615
|
||||
qcs8300
|
||||
qcs8550
|
||||
qcm2290
|
||||
qcm6490
|
||||
|
|
@ -53,6 +66,7 @@ description: |
|
|||
sa8155p
|
||||
sa8540p
|
||||
sa8775p
|
||||
sar2130p
|
||||
sc7180
|
||||
sc7280
|
||||
sc8180x
|
||||
|
|
@ -84,7 +98,10 @@ description: |
|
|||
sm8450
|
||||
sm8550
|
||||
sm8650
|
||||
sm8750
|
||||
x1e78100
|
||||
x1e80100
|
||||
x1p42100
|
||||
|
||||
There are many devices in the list below that run the standard ChromeOS
|
||||
bootloader setup and use the open source depthcharge bootloader to boot the
|
||||
|
|
@ -250,6 +267,11 @@ properties:
|
|||
- yiming,uz801-v3
|
||||
- const: qcom,msm8916
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- xiaomi,riva
|
||||
- const: qcom,msm8917
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- motorola,potter
|
||||
|
|
@ -352,6 +374,11 @@ properties:
|
|||
- qcom,ipq5332-ap-mi01.9
|
||||
- const: qcom,ipq5332
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq5424-rdp466
|
||||
- const: qcom,ipq5424
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- mikrotik,rb3011
|
||||
|
|
@ -408,6 +435,12 @@ properties:
|
|||
- qcom,qru1000-idp
|
||||
- const: qcom,qru1000
|
||||
|
||||
- description: Qualcomm AR2 Gen1 platform
|
||||
items:
|
||||
- enum:
|
||||
- qcom,qar2130p
|
||||
- const: qcom,sar2130p
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- acer,aspire1
|
||||
|
|
@ -822,8 +855,10 @@ properties:
|
|||
|
||||
- items:
|
||||
- enum:
|
||||
- huawei,gaokun3
|
||||
- lenovo,thinkpad-x13s
|
||||
- microsoft,arcata
|
||||
- microsoft,blackrock
|
||||
- qcom,sc8280xp-crd
|
||||
- qcom,sc8280xp-qrd
|
||||
- const: qcom,sc8280xp
|
||||
|
|
@ -898,6 +933,16 @@ properties:
|
|||
- const: qcom,qcs404-evb
|
||||
- const: qcom,qcs404
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs8300-ride
|
||||
- const: qcom,qcs8300
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs615-ride
|
||||
- const: qcom,qcs615
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sa8155p-adp
|
||||
|
|
@ -1064,6 +1109,18 @@ properties:
|
|||
- qcom,sm8650-qrd
|
||||
- const: qcom,sm8650
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8750-mtp
|
||||
- qcom,sm8750-qrd
|
||||
- const: qcom,sm8750
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,x1e001de-devkit
|
||||
- const: qcom,x1e001de
|
||||
- const: qcom,x1e80100
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,thinkpad-t14s
|
||||
|
|
@ -1074,6 +1131,7 @@ properties:
|
|||
- enum:
|
||||
- asus,vivobook-s15
|
||||
- dell,xps13-9345
|
||||
- hp,omnibook-x14
|
||||
- lenovo,yoga-slim7x
|
||||
- microsoft,romulus13
|
||||
- microsoft,romulus15
|
||||
|
|
@ -1081,6 +1139,11 @@ properties:
|
|||
- qcom,x1e80100-qcp
|
||||
- const: qcom,x1e80100
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,x1p42100-crd
|
||||
- const: qcom,x1p42100
|
||||
|
||||
# Board compatibles go above
|
||||
|
||||
qcom,msm-id:
|
||||
|
|
@ -1158,6 +1221,7 @@ allOf:
|
|||
- qcom,apq8026
|
||||
- qcom,apq8094
|
||||
- qcom,apq8096
|
||||
- qcom,msm8917
|
||||
- qcom,msm8939
|
||||
- qcom,msm8953
|
||||
- qcom,msm8956
|
||||
|
|
|
|||
|
|
@ -81,6 +81,17 @@ properties:
|
|||
- const: azw,beelink-a1
|
||||
- const: rockchip,rk3328
|
||||
|
||||
- description: BigTreeTech CB2 Manta M4/8P
|
||||
items:
|
||||
- const: bigtreetech,cb2-manta
|
||||
- const: bigtreetech,cb2
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: BigTreeTech Pi 2
|
||||
items:
|
||||
- const: bigtreetech,pi2
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: bq Curie 2 tablet
|
||||
items:
|
||||
- const: mundoreader,bq-curie2
|
||||
|
|
@ -167,6 +178,13 @@ properties:
|
|||
- const: engicam,px30-core
|
||||
- const: rockchip,px30
|
||||
|
||||
- description: Firefly Core-3588J-based boards
|
||||
items:
|
||||
- enum:
|
||||
- firefly,itx-3588j
|
||||
- const: firefly,core-3588j
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Firefly Core-PX30-JD4 on MB-JD4-PX30 baseboard
|
||||
items:
|
||||
- const: firefly,px30-jd4-core-mb
|
||||
|
|
@ -597,6 +615,11 @@ properties:
|
|||
- const: google,veyron
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: H96 Max V58 TV Box
|
||||
items:
|
||||
- const: haochuangyi,h96-max-v58
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Haoyu MarsBoard RK3066
|
||||
items:
|
||||
- const: haoyu,marsboard-rk3066
|
||||
|
|
@ -812,6 +835,12 @@ properties:
|
|||
- const: radxa,e20c
|
||||
- const: rockchip,rk3528
|
||||
|
||||
- description: Radxa E52C
|
||||
items:
|
||||
- const: radxa,e52c
|
||||
- const: rockchip,rk3582
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Radxa Rock
|
||||
items:
|
||||
- const: radxa,rock
|
||||
|
|
@ -1006,6 +1035,21 @@ properties:
|
|||
- const: rockchip,rk3399-sapphire-excavator
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Rockchip RK3566 BOX Evaluation Demo board
|
||||
items:
|
||||
- const: rockchip,rk3566-box-demo
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Rockchip RK3568 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3568-evb1-v10
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Rockchip RK3576 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3576-evb1-v10
|
||||
- const: rockchip,rk3576
|
||||
|
||||
- description: Rockchip RK3588 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3588-evb1-v10
|
||||
|
|
@ -1026,6 +1070,23 @@ properties:
|
|||
- const: rockchip,rk3588-toybrick-x0
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Sinovoip RK3308 Banana Pi P2 Pro
|
||||
items:
|
||||
- const: sinovoip,rk3308-bpi-p2pro
|
||||
- const: rockchip,rk3308
|
||||
|
||||
- description: Sinovoip RK3568 Banana Pi R2 Pro
|
||||
items:
|
||||
- const: sinovoip,rk3568-bpi-r2pro
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Sonoff iHost Smart Home Hub
|
||||
items:
|
||||
- const: itead,sonoff-ihost
|
||||
- enum:
|
||||
- rockchip,rv1126
|
||||
- rockchip,rv1109
|
||||
|
||||
- description: Theobroma Systems PX30-uQ7 with Haikou baseboard
|
||||
items:
|
||||
- const: tsd,px30-ringneck-haikou
|
||||
|
|
@ -1075,9 +1136,11 @@ properties:
|
|||
- const: xunlong,orangepi-3b
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Xunlong Orange Pi 5 Plus
|
||||
- description: Xunlong Orange Pi 5 Max/Plus
|
||||
items:
|
||||
- const: xunlong,orangepi-5-plus
|
||||
- enum:
|
||||
- xunlong,orangepi-5-max
|
||||
- xunlong,orangepi-5-plus
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Xunlong Orange Pi R1 Plus / LTS
|
||||
|
|
@ -1099,33 +1162,6 @@ properties:
|
|||
- const: zkmagic,a95x-z2
|
||||
- const: rockchip,rk3318
|
||||
|
||||
- description: Rockchip RK3566 BOX Evaluation Demo board
|
||||
items:
|
||||
- const: rockchip,rk3566-box-demo
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Rockchip RK3568 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3568-evb1-v10
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Sinovoip RK3308 Banana Pi P2 Pro
|
||||
items:
|
||||
- const: sinovoip,rk3308-bpi-p2pro
|
||||
- const: rockchip,rk3308
|
||||
|
||||
- description: Sinovoip RK3568 Banana Pi R2 Pro
|
||||
items:
|
||||
- const: sinovoip,rk3568-bpi-r2pro
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Sonoff iHost Smart Home Hub
|
||||
items:
|
||||
- const: itead,sonoff-ihost
|
||||
- enum:
|
||||
- rockchip,rv1126
|
||||
- rockchip,rv1109
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
|
|
|||
|
|
@ -53,11 +53,17 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-controller:
|
||||
type: object
|
||||
|
||||
reboot-mode:
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: true
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -240,6 +240,9 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- samsung,c1s # Samsung Galaxy Note20 5G (SM-N981B)
|
||||
- samsung,r8s # Samsung Galaxy S20 FE (SM-G780F)
|
||||
- samsung,x1s # Samsung Galaxy S20 5G (SM-G981B)
|
||||
- samsung,x1slte # Samsung Galaxy S20 (SM-G980F)
|
||||
- const: samsung,exynos990
|
||||
|
||||
- description: Exynos Auto v9 based boards
|
||||
|
|
|
|||
|
|
@ -91,6 +91,13 @@ properties:
|
|||
- const: dh,stm32mp153c-dhcor-som
|
||||
- const: st,stm32mp153
|
||||
|
||||
- description: Octavo OSD32MP153 System-in-Package based boards
|
||||
items:
|
||||
- enum:
|
||||
- lxa,stm32mp153c-tac-gen3 # Linux Automation TAC (Generation 3)
|
||||
- const: oct,stm32mp153x-osd32
|
||||
- const: st,stm32mp153
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- shiratech,stm32mp157a-iot-box # IoT Box
|
||||
|
|
|
|||
20
dts/upstream/Bindings/cache/qcom,llcc.yaml
vendored
20
dts/upstream/Bindings/cache/qcom,llcc.yaml
vendored
|
|
@ -20,6 +20,7 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,ipq5424-llcc
|
||||
- qcom,qcs615-llcc
|
||||
- qcom,qcs8300-llcc
|
||||
- qcom,qdu1000-llcc
|
||||
|
|
@ -42,11 +43,11 @@ properties:
|
|||
- qcom,x1e80100-llcc
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
|
||||
interrupts:
|
||||
|
|
@ -66,6 +67,21 @@ required:
|
|||
- reg-names
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,ipq5424-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC0 base register region
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -1,36 +0,0 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/chrome/google,cros-kbd-led-backlight.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ChromeOS keyboard backlight LED driver.
|
||||
|
||||
maintainers:
|
||||
- Tzung-Bi Shih <tzungbi@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: google,cros-kbd-led-backlight
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cros_ec: ec@0 {
|
||||
compatible = "google,cros-ec-spi";
|
||||
reg = <0>;
|
||||
interrupts = <15 0>;
|
||||
|
||||
kbd-led-backlight {
|
||||
compatible = "google,cros-kbd-led-backlight";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -43,6 +43,7 @@ properties:
|
|||
- atmel,sama5d4-pmc
|
||||
- microchip,sam9x60-pmc
|
||||
- microchip,sam9x7-pmc
|
||||
- microchip,sama7d65-pmc
|
||||
- microchip,sama7g5-pmc
|
||||
- const: syscon
|
||||
|
||||
|
|
@ -90,6 +91,7 @@ allOf:
|
|||
enum:
|
||||
- microchip,sam9x60-pmc
|
||||
- microchip,sam9x7-pmc
|
||||
- microchip,sama7d65-pmc
|
||||
- microchip,sama7g5-pmc
|
||||
then:
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- microchip,sam9x7-sckc
|
||||
- microchip,sama7d65-sckc
|
||||
- microchip,sama7g5-sckc
|
||||
- const: microchip,sam9x60-sckc
|
||||
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ title: Qualcomm Graphics Clock & Reset Controller
|
|||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
- Imran Shaik <quic_imrashai@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module provides the clocks, resets and power
|
||||
|
|
@ -23,10 +24,12 @@ description: |
|
|||
include/dt-bindings/clock/qcom,gpucc-sm8150.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sm8250.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sm8350.h
|
||||
include/dt-bindings/clock/qcom,qcs8300-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qcs8300-gpucc
|
||||
- qcom,sdm845-gpucc
|
||||
- qcom,sa8775p-gpucc
|
||||
- qcom,sc7180-gpucc
|
||||
|
|
|
|||
77
dts/upstream/Bindings/clock/qcom,ipq9574-cmn-pll.yaml
Normal file
77
dts/upstream/Bindings/clock/qcom,ipq9574-cmn-pll.yaml
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm CMN PLL Clock Controller on IPQ SoC
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Luo Jie <quic_luoj@quicinc.com>
|
||||
|
||||
description:
|
||||
The CMN (or common) PLL clock controller expects a reference
|
||||
input clock. This reference clock is from the on-board Wi-Fi.
|
||||
The CMN PLL supplies a number of fixed rate output clocks to
|
||||
the devices providing networking functions and to GCC. These
|
||||
networking hardware include PPE (packet process engine), PCS
|
||||
and the externally connected switch or PHY devices. The CMN
|
||||
PLL block also outputs fixed rate clocks to GCC. The PLL's
|
||||
primary function is to enable fixed rate output clocks for
|
||||
networking hardware functions used with the IPQ SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,ipq9574-cmn-pll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: The reference clock. The supported clock rates include
|
||||
25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
|
||||
- description: The AHB clock
|
||||
- description: The SYS clock
|
||||
description:
|
||||
The reference clock is the source clock of CMN PLL, which is from the
|
||||
Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
|
||||
clock registers.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref
|
||||
- const: ahb
|
||||
- const: sys
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
|
||||
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
|
||||
|
||||
cmn_pll: clock-controller@9b000 {
|
||||
compatible = "qcom,ipq9574-cmn-pll";
|
||||
reg = <0x0009b000 0x800>;
|
||||
clocks = <&cmn_pll_ref_clk>,
|
||||
<&gcc GCC_CMN_12GPLL_AHB_CLK>,
|
||||
<&gcc GCC_CMN_12GPLL_SYS_CLK>;
|
||||
clock-names = "ref", "ahb", "sys";
|
||||
#clock-cells = <1>;
|
||||
assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
|
||||
assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
|
||||
};
|
||||
...
|
||||
|
|
@ -78,6 +78,7 @@ allOf:
|
|||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
items:
|
||||
- description: Board PXO source
|
||||
- description: PLL 3 clock
|
||||
|
|
@ -87,8 +88,10 @@ allOf:
|
|||
- description: DSI phy instance 2 dsi clock
|
||||
- description: DSI phy instance 2 byte clock
|
||||
- description: HDMI phy PLL clock
|
||||
- description: LVDS PLL clock
|
||||
|
||||
clock-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: pxo
|
||||
- const: pll3
|
||||
|
|
@ -98,6 +101,7 @@ allOf:
|
|||
- const: dsi2pll
|
||||
- const: dsi2pllbyte
|
||||
- const: hdmipll
|
||||
- const: lvdspll
|
||||
|
||||
- if:
|
||||
properties:
|
||||
|
|
|
|||
59
dts/upstream/Bindings/clock/qcom,qcs615-gcc.yaml
Normal file
59
dts/upstream/Bindings/clock/qcom,qcs615-gcc.yaml
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on QCS615
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on QCS615.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,qcs615-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,qcs615-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,qcs615-gcc";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -33,6 +33,8 @@ properties:
|
|||
- qcom,rpmcc-msm8916
|
||||
- qcom,rpmcc-msm8917
|
||||
- qcom,rpmcc-msm8936
|
||||
- qcom,rpmcc-msm8937
|
||||
- qcom,rpmcc-msm8940
|
||||
- qcom,rpmcc-msm8953
|
||||
- qcom,rpmcc-msm8974
|
||||
- qcom,rpmcc-msm8976
|
||||
|
|
@ -110,6 +112,8 @@ allOf:
|
|||
- qcom,rpmcc-msm8916
|
||||
- qcom,rpmcc-msm8917
|
||||
- qcom,rpmcc-msm8936
|
||||
- qcom,rpmcc-msm8937
|
||||
- qcom,rpmcc-msm8940
|
||||
- qcom,rpmcc-msm8953
|
||||
- qcom,rpmcc-msm8974
|
||||
- qcom,rpmcc-msm8976
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qcs615-rpmh-clk
|
||||
- qcom,qdu1000-rpmh-clk
|
||||
- qcom,sa8775p-rpmh-clk
|
||||
- qcom,sar2130p-rpmh-clk
|
||||
|
|
@ -37,6 +38,7 @@ properties:
|
|||
- qcom,sm8450-rpmh-clk
|
||||
- qcom,sm8550-rpmh-clk
|
||||
- qcom,sm8650-rpmh-clk
|
||||
- qcom,sm8750-rpmh-clk
|
||||
- qcom,x1e80100-rpmh-clk
|
||||
|
||||
clocks:
|
||||
|
|
|
|||
|
|
@ -8,16 +8,20 @@ title: Qualcomm Camera Clock & Reset Controller on SA8775P
|
|||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
- Imran Shaik <quic_imrashai@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SA8775p.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,qcs8300-camcc.h
|
||||
include/dt-bindings/clock/qcom,sa8775p-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qcs8300-camcc
|
||||
- qcom,sa8775p-camcc
|
||||
|
||||
clocks:
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qcs8300-videocc
|
||||
- qcom,sa8775p-videocc
|
||||
|
||||
clocks:
|
||||
|
|
|
|||
|
|
@ -18,12 +18,6 @@ description: |
|
|||
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
|
||||
|
||||
properties:
|
||||
clocks: true
|
||||
|
||||
clock-names: true
|
||||
|
||||
reg: true
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7280-lpassaoncc
|
||||
|
|
@ -31,12 +25,24 @@ properties:
|
|||
- qcom,sc7280-lpasscorecc
|
||||
- qcom,sc7280-lpasshm
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
|
|
@ -57,8 +63,6 @@ required:
|
|||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
|
|
@ -125,6 +129,9 @@ allOf:
|
|||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
|
|
|||
|
|
@ -20,7 +20,11 @@ allOf:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-camcc
|
||||
oneOf:
|
||||
- items:
|
||||
- const: qcom,sdm670-camcc
|
||||
- const: qcom,sdm845-camcc
|
||||
- const: qcom,sdm845-camcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
46
dts/upstream/Bindings/clock/qcom,sm6115-lpasscc.yaml
Normal file
46
dts/upstream/Bindings/clock/qcom,sm6115-lpasscc.yaml
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm LPASS Core & Audio Clock Controller on SM6115
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm LPASS core and audio clock controllers provide audio-related resets
|
||||
on SM6115 and its derivatives.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,sm6115-lpasscc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6115-lpassaudiocc
|
||||
- qcom,sm6115-lpasscc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
lpass_audiocc: clock-controller@a6a9000 {
|
||||
compatible = "qcom,sm6115-lpassaudiocc";
|
||||
reg = <0x0a6a9000 0x1000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -19,7 +19,6 @@ description: |
|
|||
include/dt-bindings/clock/qcom,sm8450-camcc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-camcc.h
|
||||
include/dt-bindings/clock/qcom,sm8650-camcc.h
|
||||
include/dt-bindings/clock/qcom,x1e80100-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -29,7 +28,6 @@ properties:
|
|||
- qcom,sm8475-camcc
|
||||
- qcom,sm8550-camcc
|
||||
- qcom,sm8650-camcc
|
||||
- qcom,x1e80100-camcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ properties:
|
|||
- qcom,sm8550-gpucc
|
||||
- qcom,sm8650-gpucc
|
||||
- qcom,x1e80100-gpucc
|
||||
- qcom,x1p42100-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -12,11 +12,12 @@ maintainers:
|
|||
|
||||
description: |
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM8550.
|
||||
domains on SM8550, SM8650, SM8750 and few other platforms.
|
||||
|
||||
See also:
|
||||
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
|
||||
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
|
||||
- include/dt-bindings/clock/qcom,sm8750-dispcc.h
|
||||
- include/dt-bindings/clock/qcom,x1e80100-dispcc.h
|
||||
|
||||
properties:
|
||||
|
|
@ -25,6 +26,7 @@ properties:
|
|||
- qcom,sar2130p-dispcc
|
||||
- qcom,sm8550-dispcc
|
||||
- qcom,sm8650-dispcc
|
||||
- qcom,sm8750-dispcc
|
||||
- qcom,x1e80100-dispcc
|
||||
|
||||
clocks:
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ description: |
|
|||
See also:
|
||||
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
|
||||
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
|
||||
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -24,6 +25,7 @@ properties:
|
|||
- qcom,sar2130p-tcsr
|
||||
- qcom,sm8550-tcsr
|
||||
- qcom,sm8650-tcsr
|
||||
- qcom,sm8750-tcsr
|
||||
- qcom,x1e80100-tcsr
|
||||
- const: syscon
|
||||
|
||||
|
|
|
|||
62
dts/upstream/Bindings/clock/qcom,sm8750-gcc.yaml
Normal file
62
dts/upstream/Bindings/clock/qcom,sm8750-gcc.yaml
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8750-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on SM8750
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM8750
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8750-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board Always On XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 0 Pipe clock source
|
||||
- description: UFS Phy Rx symbol 0 clock source
|
||||
- description: UFS Phy Rx symbol 1 clock source
|
||||
- description: UFS Phy Tx symbol 0 clock source
|
||||
- description: USB3 Phy wrapper pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,sm8750-gcc";
|
||||
reg = <0x00100000 0x001f4200>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>,
|
||||
<&pcie0_phy>,
|
||||
<&ufs_mem_phy 0>,
|
||||
<&ufs_mem_phy 1>,
|
||||
<&ufs_mem_phy 2>,
|
||||
<&usb_1_qmpphy>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
74
dts/upstream/Bindings/clock/qcom,x1e80100-camcc.yaml
Normal file
74
dts/upstream/Bindings/clock/qcom,x1e80100-camcc.yaml
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,x1e80100-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller on x1e80100
|
||||
|
||||
maintainers:
|
||||
- Bryan O'Donoghue <bryan.odonoghue@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on x1e80100.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,x1e80100-camcc.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,x1e80100-camcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Camera AHB clock from GCC
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: A phandle to the MXC power-domain
|
||||
- description: A phandle to the MMCX power-domain
|
||||
|
||||
required-opps:
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle to an OPP node describing MMCX performance points.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
clock-controller@ade0000 {
|
||||
compatible = "qcom,x1e80100-camcc";
|
||||
reg = <0xade0000 0x20000>;
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
power-domains = <&rpmhpd RPMHPD_MXC>,
|
||||
<&rpmhpd RPMHPD_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -17,7 +17,11 @@ description: |
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,x1e80100-gcc
|
||||
oneOf:
|
||||
- items:
|
||||
- const: qcom,x1p42100-gcc
|
||||
- const: qcom,x1e80100-gcc
|
||||
- const: qcom,x1e80100-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,5l35023
|
||||
- renesas,5p35023
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -4,19 +4,22 @@
|
|||
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
|
||||
title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
|
||||
|
||||
maintainers:
|
||||
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
||||
|
||||
description:
|
||||
On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
|
||||
and control of clock signals for the IP modules, generation and control of resets,
|
||||
and control over booting, low power consumption and power supply domains.
|
||||
On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
|
||||
generation and control of clock signals for the IP modules, generation and
|
||||
control of resets, and control over booting, low power consumption and power
|
||||
supply domains.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,r9a09g057-cpg
|
||||
enum:
|
||||
- renesas,r9a09g047-cpg # RZ/G3E
|
||||
- renesas,r9a09g057-cpg # RZ/V2H
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -37,7 +40,7 @@ properties:
|
|||
description: |
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
and a core clock reference, as defined in
|
||||
<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
|
||||
<dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
|
||||
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
|
||||
a module number. The module number is calculated as the CLKON register
|
||||
offset index multiplied by 16, plus the actual bit in the register
|
||||
|
|
|
|||
121
dts/upstream/Bindings/clock/samsung,exynos990-clock.yaml
Normal file
121
dts/upstream/Bindings/clock/samsung,exynos990-clock.yaml
Normal file
|
|
@ -0,0 +1,121 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos990-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos990 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Igor Belwon <igor.belwon@mentallysanemainliners.org>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description: |
|
||||
Exynos990 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. The root clock in that root tree
|
||||
is an external clock: OSCCLK (26 MHz). This external clock must be defined
|
||||
as a fixed-rate clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynos990.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos990-cmu-hsi0
|
||||
- samsung,exynos990-cmu-top
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos990-cmu-hsi0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_HSI0 BUS clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 USB31DRD clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 DPGTC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: usb31drd
|
||||
- const: usbdp_debug
|
||||
- const: dpgtc
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos990-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynos990.h>
|
||||
|
||||
cmu_hsi0: clock-controller@10a00000 {
|
||||
compatible = "samsung,exynos990-cmu-hsi0";
|
||||
reg = <0x10a00000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&oscclk>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
|
||||
clock-names = "oscclk",
|
||||
"bus",
|
||||
"usb31drd",
|
||||
"usbdp_debug",
|
||||
"dpgtc";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,138 +0,0 @@
|
|||
STMicroelectronics STM32 Reset and Clock Controller
|
||||
===================================================
|
||||
|
||||
The RCC IP is both a reset and a clock controller.
|
||||
|
||||
Please refer to clock-bindings.txt for common clock controller binding usage.
|
||||
Please also refer to reset.txt for common reset controller binding usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be:
|
||||
"st,stm32f42xx-rcc"
|
||||
"st,stm32f469-rcc"
|
||||
"st,stm32f746-rcc"
|
||||
"st,stm32f769-rcc"
|
||||
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- #reset-cells: 1, see below
|
||||
- #clock-cells: 2, device nodes should specify the clock in their "clocks"
|
||||
property, containing a phandle to the clock device node, an index selecting
|
||||
between gated clocks and other clocks and an index specifying the clock to
|
||||
use.
|
||||
- clocks: External oscillator clock phandle
|
||||
- high speed external clock signal (HSE)
|
||||
- external I2S clock (I2S_CKIN)
|
||||
|
||||
Example:
|
||||
|
||||
rcc: rcc@40023800 {
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <2>
|
||||
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
|
||||
reg = <0x40023800 0x400>;
|
||||
clocks = <&clk_hse>, <&clk_i2s_ckin>;
|
||||
};
|
||||
|
||||
Specifying gated clocks
|
||||
=======================
|
||||
|
||||
The primary index must be set to 0.
|
||||
|
||||
The secondary index is the bit number within the RCC register bank, starting
|
||||
from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
|
||||
|
||||
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
|
||||
Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
|
||||
|
||||
To simplify the usage and to share bit definition with the reset and clock
|
||||
drivers of the RCC IP, macros are available to generate the index in
|
||||
human-readble format.
|
||||
|
||||
For STM32F4 series, the macro are available here:
|
||||
- include/dt-bindings/mfd/stm32f4-rcc.h
|
||||
|
||||
Example:
|
||||
|
||||
/* Gated clock, AHB1 bit 0 (GPIOA) */
|
||||
... {
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
|
||||
};
|
||||
|
||||
/* Gated clock, AHB2 bit 4 (CRYP) */
|
||||
... {
|
||||
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
|
||||
};
|
||||
|
||||
Specifying other clocks
|
||||
=======================
|
||||
|
||||
The primary index must be set to 1.
|
||||
|
||||
The secondary index is bound with the following magic numbers:
|
||||
|
||||
0 SYSTICK
|
||||
1 FCLK
|
||||
2 CLK_LSI (low-power clock source)
|
||||
3 CLK_LSE (generated from a 32.768 kHz low-speed external
|
||||
crystal or ceramic resonator)
|
||||
4 CLK_HSE_RTC (HSE division factor for RTC clock)
|
||||
5 CLK_RTC (real-time clock)
|
||||
6 PLL_VCO_I2S (vco frequency of I2S pll)
|
||||
7 PLL_VCO_SAI (vco frequency of SAI pll)
|
||||
8 CLK_LCD (LCD-TFT)
|
||||
9 CLK_I2S (I2S clocks)
|
||||
10 CLK_SAI1 (audio clocks)
|
||||
11 CLK_SAI2
|
||||
12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor)
|
||||
13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor)
|
||||
|
||||
14 CLK_HSI (Internal ocscillator clock)
|
||||
15 CLK_SYSCLK (System Clock)
|
||||
16 CLK_HDMI_CEC (HDMI-CEC clock)
|
||||
17 CLK_SPDIF (SPDIF-Rx clock)
|
||||
18 CLK_USART1 (U(s)arts clocks)
|
||||
19 CLK_USART2
|
||||
20 CLK_USART3
|
||||
21 CLK_UART4
|
||||
22 CLK_UART5
|
||||
23 CLK_USART6
|
||||
24 CLK_UART7
|
||||
25 CLK_UART8
|
||||
26 CLK_I2C1 (I2S clocks)
|
||||
27 CLK_I2C2
|
||||
28 CLK_I2C3
|
||||
29 CLK_I2C4
|
||||
30 CLK_LPTIMER (LPTimer1 clock)
|
||||
31 CLK_PLL_SRC
|
||||
32 CLK_DFSDM1
|
||||
33 CLK_ADFSDM1
|
||||
34 CLK_F769_DSI
|
||||
)
|
||||
|
||||
Example:
|
||||
|
||||
/* Misc clock, FCLK */
|
||||
... {
|
||||
clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
|
||||
};
|
||||
|
||||
|
||||
Specifying softreset control of devices
|
||||
=======================================
|
||||
|
||||
Device nodes should specify the reset channel required in their "resets"
|
||||
property, containing a phandle to the reset device node and an index specifying
|
||||
which channel to use.
|
||||
The index is the bit number within the RCC registers bank, starting from RCC
|
||||
base address.
|
||||
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
|
||||
Where bit_offset is the bit offset within the register.
|
||||
For example, for CRC reset:
|
||||
crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
|
||||
|
||||
example:
|
||||
|
||||
timer2 {
|
||||
resets = <&rcc STM32F4_APB1_RESET(TIM2)>;
|
||||
};
|
||||
144
dts/upstream/Bindings/clock/st,stm32-rcc.yaml
Normal file
144
dts/upstream/Bindings/clock/st,stm32-rcc.yaml
Normal file
|
|
@ -0,0 +1,144 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 Reset Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Dario Binacchi <dario.binacchi@amarulasolutions.com>
|
||||
|
||||
description: |
|
||||
The RCC IP is both a reset and a clock controller.
|
||||
The reset phandle argument is the bit number within the RCC registers bank,
|
||||
starting from RCC base address.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32f42xx-rcc
|
||||
- st,stm32f746-rcc
|
||||
- st,stm32h743-rcc
|
||||
- const: st,stm32-rcc
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32f469-rcc
|
||||
- const: st,stm32f42xx-rcc
|
||||
- const: st,stm32-rcc
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32f769-rcc
|
||||
- const: st,stm32f746-rcc
|
||||
- const: st,stm32-rcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#clock-cells':
|
||||
enum: [1, 2]
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
st,syscfg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to system configuration controller. It can be used to control the
|
||||
power domain circuitry.
|
||||
|
||||
st,ssc-modfreq-hz:
|
||||
description:
|
||||
The modulation frequency for main PLL (in Hz)
|
||||
|
||||
st,ssc-moddepth-permyriad:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
The modulation rate for main PLL (in permyriad, i.e. 0.01%)
|
||||
minimum: 25
|
||||
maximum: 200
|
||||
|
||||
st,ssc-modmethod:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description:
|
||||
The modulation techniques for main PLL.
|
||||
items:
|
||||
enum:
|
||||
- center-spread
|
||||
- down-spread
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#reset-cells'
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
- st,syscfg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: st,stm32h743-rcc
|
||||
then:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description: |
|
||||
The clock index for the specified type.
|
||||
clocks:
|
||||
items:
|
||||
- description: high speed external (HSE) clock input
|
||||
- description: low speed external (LSE) clock input
|
||||
- description: Inter-IC sound (I2S) clock input
|
||||
st,ssc-modfreq-hz: false
|
||||
st,ssc-moddepth-permyriad: false
|
||||
st,ssc-modmethod: false
|
||||
|
||||
else:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 2
|
||||
description: |
|
||||
- The first cell is the clock type, possible values are 0 for
|
||||
gated clocks and 1 otherwise.
|
||||
- The second cell is the clock index for the specified type.
|
||||
clocks:
|
||||
items:
|
||||
- description: high speed external (HSE) clock input
|
||||
- description: Inter-IC sound (I2S) clock input
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Reset and Clock Control Module node:
|
||||
- |
|
||||
clock-controller@40023800 {
|
||||
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
|
||||
reg = <0x40023800 0x400>;
|
||||
#clock-cells = <2>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&clk_hse>, <&clk_i2s_ckin>;
|
||||
st,syscfg = <&pwrcfg>;
|
||||
st,ssc-modfreq-hz = <10000>;
|
||||
st,ssc-moddepth-permyriad = <200>;
|
||||
st,ssc-modmethod = "center-spread";
|
||||
};
|
||||
- |
|
||||
clock-controller@58024400 {
|
||||
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
|
||||
reg = <0x58024400 0x400>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
|
||||
st,syscfg = <&pwrcfg>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -21,7 +21,7 @@ description: |
|
|||
=================
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/stm32mp1-clks.h header and can be used in device
|
||||
include/dt-bindings/clock/stm32mp1-clks.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Specifying softreset control of devices
|
||||
|
|
@ -40,8 +40,8 @@ description: |
|
|||
= 0x180 / 4 * 32 + 0 = 3072
|
||||
|
||||
The list of valid indices for STM32MP1 is available in:
|
||||
include/dt-bindings/reset-controller/stm32mp1-resets.h
|
||||
include/dt-bindings/reset-controller/stm32mp13-resets.h
|
||||
include/dt-bindings/reset/stm32mp1-resets.h
|
||||
include/dt-bindings/reset/stm32mp13-resets.h
|
||||
|
||||
This file implements defines like:
|
||||
#define LTDC_R 3072
|
||||
|
|
|
|||
|
|
@ -1,55 +0,0 @@
|
|||
Binding for TI composite clock.
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped composite clock with multiple different sub-types;
|
||||
|
||||
a multiplexer clock with multiple input clock signals or parents, one
|
||||
of which can be selected as output, this behaves exactly as [2]
|
||||
|
||||
an adjustable clock rate divider, this behaves exactly as [3]
|
||||
|
||||
a gating function which can be used to enable and disable the output
|
||||
clock, this behaves exactly as [4]
|
||||
|
||||
The binding must provide a list of the component clocks that shall be
|
||||
merged to this clock. The component clocks shall be of one of the
|
||||
"ti,*composite*-clock" types.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
|
||||
[3] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml
|
||||
[4] Documentation/devicetree/bindings/clock/ti/gate.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be: "ti,composite-clock"
|
||||
- clocks : link phandles of component clocks
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
|
||||
Examples:
|
||||
|
||||
usb_l4_gate_ick: usb_l4_gate_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <5>;
|
||||
reg = <0x0a10>;
|
||||
};
|
||||
|
||||
usb_l4_div_ick: usb_l4_div_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
ti,max-div = <1>;
|
||||
reg = <0x0a40>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
usb_l4_ick: usb_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
|
||||
};
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
Binding for Texas Instruments gate clock.
|
||||
|
||||
This binding uses the common clock binding[1]. This clock is
|
||||
quite much similar to the basic gate-clock [2], however,
|
||||
it supports a number of additional features. If no register
|
||||
is provided for this clock, the code assumes that a clockdomain
|
||||
will be controlled instead and the corresponding hw-ops for
|
||||
that is used.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
|
||||
[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of:
|
||||
"ti,gate-clock" - basic gate clock
|
||||
"ti,wait-gate-clock" - gate clock which waits until clock is active before
|
||||
returning from clk_enable()
|
||||
"ti,dss-gate-clock" - gate clock with DSS specific hardware handling
|
||||
"ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
|
||||
"ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
|
||||
clock directly from a clockdomain, see [3] how
|
||||
to map clockdomains properly
|
||||
"ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
|
||||
required for a hardware errata
|
||||
"ti,composite-gate-clock" - composite gate clock, to be part of composite
|
||||
clock
|
||||
"ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
|
||||
for clock to be active before returning
|
||||
from clk_enable()
|
||||
- #clock-cells : from common clock binding; shall be set to 0
|
||||
- clocks : link to phandle of parent clock
|
||||
- reg : offset for register controlling adjustable gate, not needed for
|
||||
ti,clkdm-gate-clock type
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,bit-shift : bit shift for programming the clock gate, invalid for
|
||||
ti,clkdm-gate-clock type
|
||||
- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
|
||||
gates the clock and clearing the bit ungates the clock.
|
||||
|
||||
Examples:
|
||||
mmchs2_fck: mmchs2_fck@48004a00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <25>;
|
||||
};
|
||||
|
||||
uart4_fck_am35xx: uart4_fck_am35xx {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_48m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
|
||||
dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
reg = <0x0e00>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
emac_ick: emac_ick@4800259c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
clocks = <&ipss_ick>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
emu_src_ck: emu_src_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,clkdm-gate-clock";
|
||||
clocks = <&emu_src_mux_ck>;
|
||||
};
|
||||
|
||||
dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m2x2_mul_ck>;
|
||||
ti,bit-shift = <0x1b>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
vlynq_gate_fck: vlynq_gate_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&core_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
reg = <0x0200>;
|
||||
};
|
||||
|
||||
sys_clkout2_src_gate: sys_clkout2_src_gate {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clocks = <&core_ck>;
|
||||
ti,bit-shift = <15>;
|
||||
reg = <0x0070>;
|
||||
};
|
||||
82
dts/upstream/Bindings/clock/ti/ti,composite-clock.yaml
Normal file
82
dts/upstream/Bindings/clock/ti/ti,composite-clock.yaml
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti/ti,composite-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments composite clock
|
||||
|
||||
maintainers:
|
||||
- Tero Kristo <kristo@kernel.org>
|
||||
|
||||
description: |
|
||||
*Deprecated design pattern: one node per clock*
|
||||
|
||||
This binding assumes a register-mapped composite clock with multiple
|
||||
different sub-types:
|
||||
|
||||
a multiplexer clock with multiple input clock signals or parents, one
|
||||
of which can be selected as output, this behaves exactly as [1].
|
||||
|
||||
an adjustable clock rate divider, this behaves exactly as [2].
|
||||
|
||||
a gating function which can be used to enable and disable the output
|
||||
clock, this behaves exactly as [3].
|
||||
|
||||
The binding must provide a list of the component clocks that shall be
|
||||
merged to this clock. The component clocks shall be of one of the
|
||||
"ti,*composite*-clock" types.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
|
||||
[2] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml
|
||||
[3] Documentation/devicetree/bindings/clock/ti/ti,gate-clock.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ti,composite-clock
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clocks: true
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb_l4_gate_ick: clock-controller@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <5>;
|
||||
reg = <0x0a10>;
|
||||
};
|
||||
|
||||
usb_l4_div_ick: clock-controller@a40 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
ti,max-div = <1>;
|
||||
reg = <0x0a40>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
};
|
||||
|
||||
clock-controller {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
|
||||
};
|
||||
125
dts/upstream/Bindings/clock/ti/ti,gate-clock.yaml
Normal file
125
dts/upstream/Bindings/clock/ti/ti,gate-clock.yaml
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti/ti,gate-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments gate clock
|
||||
|
||||
maintainers:
|
||||
- Tero Kristo <kristo@kernel.org>
|
||||
|
||||
description: |
|
||||
*Deprecated design pattern: one node per clock*
|
||||
|
||||
This clock is quite much similar to the basic gate-clock [1], however,
|
||||
it supports a number of additional features. If no register
|
||||
is provided for this clock, the code assumes that a clockdomain
|
||||
will be controlled instead and the corresponding hw-ops for
|
||||
that is used.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
|
||||
[2] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,gate-clock # basic gate clock
|
||||
- ti,wait-gate-clock # gate clock which waits until clock is
|
||||
# active before returning from clk_enable()
|
||||
- ti,dss-gate-clock # gate clock with DSS specific hardware
|
||||
# handling
|
||||
- ti,am35xx-gate-clock # gate clock with AM35xx specific hardware
|
||||
# handling
|
||||
- ti,clkdm-gate-clock # clockdomain gate clock, which derives its
|
||||
# functional clock directly from a
|
||||
# clockdomain, see [2] how to map
|
||||
# clockdomains properly
|
||||
- ti,hsdiv-gate-clock # gate clock with OMAP36xx specific hardware
|
||||
# handling, required for a hardware errata
|
||||
- ti,composite-gate-clock # composite gate clock, to be part of
|
||||
# composite clock
|
||||
- ti,composite-no-wait-gate-clock # composite gate clock that does not
|
||||
# wait for clock to be active before
|
||||
# returning from clk_enable()
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clocks: true
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ti,bit-shift:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Number of bits to shift the bit-mask
|
||||
maximum: 31
|
||||
default: 0
|
||||
|
||||
ti,set-bit-to-disable:
|
||||
type: boolean
|
||||
description:
|
||||
Inverts default gate programming. Setting the bit
|
||||
gates the clock and clearing the bit ungates the clock.
|
||||
|
||||
ti,set-rate-parent:
|
||||
type: boolean
|
||||
description:
|
||||
clk_set_rate is propagated to parent clock,
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,clkdm-gate-clock
|
||||
then:
|
||||
properties:
|
||||
reg: false
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
else:
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-controller@a00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <25>;
|
||||
};
|
||||
|
||||
clock-controller@d00 {
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
reg = <0x0d00>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&dpll4_m2x2_mul_ck>;
|
||||
ti,bit-shift = <0x1b>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
clock-controller {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,clkdm-gate-clock";
|
||||
clocks = <&emu_src_mux_ck>;
|
||||
};
|
||||
|
||||
59
dts/upstream/Bindings/clock/xlnx,vcu.yaml
Normal file
59
dts/upstream/Bindings/clock/xlnx,vcu.yaml
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: LogicoreIP designed compatible with Xilinx ZYNQ family.
|
||||
|
||||
maintainers:
|
||||
- Rohit Visavalia <rohit.visavalia@amd.com>
|
||||
|
||||
description:
|
||||
LogicoreIP design to provide the isolation between processing system
|
||||
and programmable logic. Also provides the list of register set to configure
|
||||
the frequency.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- xlnx,vcu
|
||||
- xlnx,vcu-logicoreip-1.0
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: pll ref clocksource
|
||||
- description: aclk
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pll_ref
|
||||
- const: aclk
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
fpga {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
xlnx_vcu: vcu@a0040000 {
|
||||
compatible = "xlnx,vcu-logicoreip-1.0";
|
||||
reg = <0x0 0xa0040000 0x0 0x1000>;
|
||||
reset-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&si570_1>, <&clkc 71>;
|
||||
clock-names = "pll_ref", "aclk";
|
||||
};
|
||||
};
|
||||
|
|
@ -293,6 +293,13 @@ properties:
|
|||
PD negotiation till BC1.2 detection completes.
|
||||
default: 0
|
||||
|
||||
pd-revision:
|
||||
description: Specifies the maximum USB PD revision and version supported by
|
||||
the connector. This property is specified in the following order;
|
||||
<revision_major, revision_minor, version_major, version_minor>.
|
||||
$ref: /schemas/types.yaml#/definitions/uint8-array
|
||||
maxItems: 4
|
||||
|
||||
dependencies:
|
||||
sink-vdos-v1: [ sink-vdos ]
|
||||
sink-vdos: [ sink-vdos-v1 ]
|
||||
|
|
|
|||
55
dts/upstream/Bindings/cpufreq/airoha,en7581-cpufreq.yaml
Normal file
55
dts/upstream/Bindings/cpufreq/airoha,en7581-cpufreq.yaml
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cpufreq/airoha,en7581-cpufreq.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Airoha EN7581 CPUFreq
|
||||
|
||||
maintainers:
|
||||
- Christian Marangi <ansuelsmth@gmail.com>
|
||||
|
||||
description: |
|
||||
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMC commands
|
||||
to ATF.
|
||||
|
||||
A virtual clock is exposed. This virtual clock is a get-only clock and
|
||||
is used to expose the current global CPU clock. The frequency info comes
|
||||
by the output of the SMC command that reports the clock in MHz.
|
||||
|
||||
The SMC sets the CPU clock by providing an index, this is modelled as
|
||||
performance states in a power domain.
|
||||
|
||||
CPUs can't be individually scaled as the CPU frequency is shared across
|
||||
all CPUs and is global.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: airoha,en7581-cpufreq
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
- operating-points-v2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
performance-domain {
|
||||
compatible = "airoha,en7581-cpufreq";
|
||||
|
||||
operating-points-v2 = <&cpu_smcc_opp_table>;
|
||||
|
||||
#power-domain-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
|
@ -24,9 +24,17 @@ properties:
|
|||
- apple,t8112-cluster-cpufreq
|
||||
- const: apple,cluster-cpufreq
|
||||
- items:
|
||||
- const: apple,t6000-cluster-cpufreq
|
||||
- enum:
|
||||
- apple,s8000-cluster-cpufreq
|
||||
- apple,t8010-cluster-cpufreq
|
||||
- apple,t8015-cluster-cpufreq
|
||||
- apple,t6000-cluster-cpufreq
|
||||
- const: apple,t8103-cluster-cpufreq
|
||||
- const: apple,cluster-cpufreq
|
||||
- items:
|
||||
- const: apple,t7000-cluster-cpufreq
|
||||
- const: apple,s5l8960x-cluster-cpufreq
|
||||
- const: apple,s5l8960x-cluster-cpufreq
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -13,12 +13,14 @@ properties:
|
|||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,qcs8300-inline-crypto-engine
|
||||
- qcom,sa8775p-inline-crypto-engine
|
||||
- qcom,sc7180-inline-crypto-engine
|
||||
- qcom,sc7280-inline-crypto-engine
|
||||
- qcom,sm8450-inline-crypto-engine
|
||||
- qcom,sm8550-inline-crypto-engine
|
||||
- qcom,sm8650-inline-crypto-engine
|
||||
- qcom,sm8750-inline-crypto-engine
|
||||
- const: qcom,inline-crypto-engine
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -17,12 +17,17 @@ properties:
|
|||
- qcom,prng-ee # 8996 and later using EE
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq5332-trng
|
||||
- qcom,ipq5424-trng
|
||||
- qcom,ipq9574-trng
|
||||
- qcom,qcs8300-trng
|
||||
- qcom,sa8255p-trng
|
||||
- qcom,sa8775p-trng
|
||||
- qcom,sc7280-trng
|
||||
- qcom,sm8450-trng
|
||||
- qcom,sm8550-trng
|
||||
- qcom,sm8650-trng
|
||||
- qcom,sm8750-trng
|
||||
- const: qcom,trng
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Qualcomm crypto engine driver
|
||||
|
||||
maintainers:
|
||||
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
|
||||
description:
|
||||
This document defines the binding for the QCE crypto
|
||||
|
|
@ -44,6 +45,7 @@ properties:
|
|||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs8300-qce
|
||||
- qcom,sa8775p-qce
|
||||
- qcom,sc7280-qce
|
||||
- qcom,sm6350-qce
|
||||
|
|
@ -52,6 +54,7 @@ properties:
|
|||
- qcom,sm8450-qce
|
||||
- qcom,sm8550-qce
|
||||
- qcom,sm8650-qce
|
||||
- qcom,sm8750-qce
|
||||
- const: qcom,sm8150-qce
|
||||
- const: qcom,qce
|
||||
|
||||
|
|
|
|||
|
|
@ -148,10 +148,10 @@ examples:
|
|||
|
||||
/* TMDS Output */
|
||||
hdmi_tx_tmds_port: port@1 {
|
||||
reg = <1>;
|
||||
reg = <1>;
|
||||
|
||||
hdmi_tx_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
hdmi_tx_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,6 +14,8 @@ properties:
|
|||
enum:
|
||||
- brcm,bcm2711-hdmi0
|
||||
- brcm,bcm2711-hdmi1
|
||||
- brcm,bcm2712-hdmi0
|
||||
- brcm,bcm2712-hdmi1
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ properties:
|
|||
compatible:
|
||||
enum:
|
||||
- brcm,bcm2711-hvs
|
||||
- brcm,bcm2712-hvs
|
||||
- brcm,bcm2835-hvs
|
||||
|
||||
reg:
|
||||
|
|
@ -36,7 +37,9 @@ if:
|
|||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,bcm2711-hvs
|
||||
enum:
|
||||
- brcm,bcm2711-hvs
|
||||
- brcm,bcm2712-hvs
|
||||
|
||||
then:
|
||||
required:
|
||||
|
|
|
|||
|
|
@ -20,6 +20,9 @@ properties:
|
|||
- brcm,bcm2711-pixelvalve2
|
||||
- brcm,bcm2711-pixelvalve3
|
||||
- brcm,bcm2711-pixelvalve4
|
||||
- brcm,bcm2712-pixelvalve0
|
||||
- brcm,bcm2712-pixelvalve1
|
||||
- brcm,bcm2712-pixelvalve2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -11,7 +11,10 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,bcm2835-txp
|
||||
enum:
|
||||
- brcm,bcm2712-mop
|
||||
- brcm,bcm2712-moplet
|
||||
- brcm,bcm2835-txp
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ properties:
|
|||
compatible:
|
||||
enum:
|
||||
- brcm,bcm2711-vc5
|
||||
- brcm,bcm2712-vc6
|
||||
- brcm,bcm2835-vc4
|
||||
- brcm,cygnus-vc4
|
||||
|
||||
|
|
|
|||
|
|
@ -82,21 +82,21 @@ examples:
|
|||
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
|
||||
reg-io-width = <1>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi_tx_from_pvi: endpoint {
|
||||
remote-endpoint = <&pvi_to_hdmi_tx>;
|
||||
};
|
||||
};
|
||||
endpoint {
|
||||
remote-endpoint = <&pvi_to_hdmi_tx>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
hdmi_tx_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ properties:
|
|||
enum:
|
||||
- renesas,r8a779a0-dsi-csi2-tx # for V3U
|
||||
- renesas,r8a779g0-dsi-csi2-tx # for V4H
|
||||
- renesas,r8a779h0-dsi-csi2-tx # for V4M
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -27,7 +27,9 @@ properties:
|
|||
- fsl,imx8mm-mipi-dsim
|
||||
- fsl,imx8mp-mipi-dsim
|
||||
- items:
|
||||
- const: fsl,imx8mn-mipi-dsim
|
||||
- enum:
|
||||
- fsl,imx7d-mipi-dsim
|
||||
- fsl,imx8mn-mipi-dsim
|
||||
- const: fsl,imx8mm-mipi-dsim
|
||||
|
||||
reg:
|
||||
|
|
@ -241,40 +243,40 @@ examples:
|
|||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
dsi@13900000 {
|
||||
compatible = "samsung,exynos5433-mipi-dsi";
|
||||
reg = <0x13900000 0xC0>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&mipi_phy 1>;
|
||||
phy-names = "dsim";
|
||||
clocks = <&cmu_disp CLK_PCLK_DSIM0>,
|
||||
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
|
||||
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
|
||||
<&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
|
||||
<&cmu_disp CLK_SCLK_DSIM0>;
|
||||
clock-names = "bus_clk",
|
||||
"phyclk_mipidphy0_bitclkdiv8",
|
||||
"phyclk_mipidphy0_rxclkesc0",
|
||||
"sclk_rgb_vclk_to_dsim0",
|
||||
"sclk_mipi";
|
||||
power-domains = <&pd_disp>;
|
||||
vddcore-supply = <&ldo6_reg>;
|
||||
vddio-supply = <&ldo7_reg>;
|
||||
samsung,burst-clock-frequency = <512000000>;
|
||||
samsung,esc-clock-frequency = <16000000>;
|
||||
samsung,pll-clock-frequency = <24000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&te_irq>;
|
||||
compatible = "samsung,exynos5433-mipi-dsi";
|
||||
reg = <0x13900000 0xC0>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&mipi_phy 1>;
|
||||
phy-names = "dsim";
|
||||
clocks = <&cmu_disp CLK_PCLK_DSIM0>,
|
||||
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
|
||||
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
|
||||
<&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
|
||||
<&cmu_disp CLK_SCLK_DSIM0>;
|
||||
clock-names = "bus_clk",
|
||||
"phyclk_mipidphy0_bitclkdiv8",
|
||||
"phyclk_mipidphy0_rxclkesc0",
|
||||
"sclk_rgb_vclk_to_dsim0",
|
||||
"sclk_mipi";
|
||||
power-domains = <&pd_disp>;
|
||||
vddcore-supply = <&ldo6_reg>;
|
||||
vddio-supply = <&ldo7_reg>;
|
||||
samsung,burst-clock-frequency = <512000000>;
|
||||
samsung,esc-clock-frequency = <16000000>;
|
||||
samsung,pll-clock-frequency = <24000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&te_irq>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
dsi_to_mic: endpoint {
|
||||
remote-endpoint = <&mic_to_dsi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
dsi_to_mic: endpoint {
|
||||
remote-endpoint = <&mic_to_dsi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -80,12 +80,12 @@ properties:
|
|||
- const: 4
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for LVDS Channel-A output (panel or bridge).
|
||||
$ref: '#/$defs/lvds-port'
|
||||
|
||||
port@3:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for LVDS Channel-B output (panel or bridge).
|
||||
$ref: '#/$defs/lvds-port'
|
||||
|
||||
required:
|
||||
- port@0
|
||||
|
|
@ -96,6 +96,36 @@ required:
|
|||
- reg
|
||||
- ports
|
||||
|
||||
$defs:
|
||||
lvds-port:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
ti,lvds-termination-ohms:
|
||||
description: The value of near end differential termination in ohms.
|
||||
enum: [100, 200]
|
||||
default: 200
|
||||
|
||||
ti,lvds-vod-swing-clock-microvolt:
|
||||
description: LVDS diferential output voltage <min max> for clock
|
||||
lanes in microvolts.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
ti,lvds-vod-swing-data-microvolt:
|
||||
description: LVDS diferential output voltage <min max> for data
|
||||
lanes in microvolts.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -104,30 +104,30 @@ examples:
|
|||
#size-cells = <2>;
|
||||
|
||||
aal@14015000 {
|
||||
compatible = "mediatek,mt8173-disp-aal";
|
||||
reg = <0 0x14015000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_AAL>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
|
||||
compatible = "mediatek,mt8173-disp-aal";
|
||||
reg = <0 0x14015000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_AAL>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
aal0_in: endpoint {
|
||||
remote-endpoint = <&ccorr0_out>;
|
||||
};
|
||||
};
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&ccorr0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
aal0_out: endpoint {
|
||||
remote-endpoint = <&gamma0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&gamma0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ properties:
|
|||
- mediatek,mt8173-disp-ovl
|
||||
- mediatek,mt8183-disp-ovl
|
||||
- mediatek,mt8192-disp-ovl
|
||||
- mediatek,mt8195-disp-ovl
|
||||
- mediatek,mt8195-mdp3-ovl
|
||||
- items:
|
||||
- enum:
|
||||
|
|
@ -36,16 +37,17 @@ properties:
|
|||
- enum:
|
||||
- mediatek,mt6795-disp-ovl
|
||||
- const: mediatek,mt8173-disp-ovl
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-disp-ovl
|
||||
- mediatek,mt8195-disp-ovl
|
||||
- const: mediatek,mt8183-disp-ovl
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-ovl
|
||||
- mediatek,mt8365-disp-ovl
|
||||
- const: mediatek,mt8192-disp-ovl
|
||||
- items:
|
||||
- const: mediatek,mt8188-disp-ovl
|
||||
- const: mediatek,mt8195-disp-ovl
|
||||
- items:
|
||||
- const: mediatek,mt8188-mdp3-ovl
|
||||
- const: mediatek,mt8195-mdp3-ovl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ title: MSM Display Port Controller
|
|||
|
||||
maintainers:
|
||||
- Kuogee Hsieh <quic_khsieh@quicinc.com>
|
||||
- Abhinav Kumar <quic_abhinavk@quicinc.com>
|
||||
|
||||
description: |
|
||||
Device tree bindings for DisplayPort host controller for MSM targets
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ properties:
|
|||
- qcom,sdm845-dsi-ctrl
|
||||
- qcom,sm6115-dsi-ctrl
|
||||
- qcom,sm6125-dsi-ctrl
|
||||
- qcom,sm6150-dsi-ctrl
|
||||
- qcom,sm6350-dsi-ctrl
|
||||
- qcom,sm6375-dsi-ctrl
|
||||
- qcom,sm7150-dsi-ctrl
|
||||
|
|
@ -349,6 +350,7 @@ allOf:
|
|||
enum:
|
||||
- qcom,sc7180-dsi-ctrl
|
||||
- qcom,sc7280-dsi-ctrl
|
||||
- qcom,sm6150-dsi-ctrl
|
||||
- qcom,sm7150-dsi-ctrl
|
||||
- qcom,sm8150-dsi-ctrl
|
||||
- qcom,sm8250-dsi-ctrl
|
||||
|
|
@ -416,63 +418,63 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
|
||||
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
qcom,te-source = "mdp_vsync_e";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
qcom,te-source = "mdp_vsync_e";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -74,28 +74,28 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-10nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-10nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
|
||||
qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
|
||||
qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
|
||||
qcom,phy-drive-ldo-level = <400>;
|
||||
};
|
||||
qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
|
||||
qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
|
||||
qcom,phy-drive-ldo-level = <400>;
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ properties:
|
|||
- qcom,dsi-phy-14nm-660
|
||||
- qcom,dsi-phy-14nm-8953
|
||||
- qcom,sm6125-dsi-phy-14nm
|
||||
- qcom,sm6150-dsi-phy-14nm
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
|
@ -55,24 +56,24 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-14nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-14nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vcca-supply = <&vcca_reg>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
vcca-supply = <&vcca_reg>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -45,26 +45,26 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-20nm";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
reg-names = "dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-20nm";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
reg-names = "dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vcca-supply = <&vcca_reg>;
|
||||
vddio-supply = <&vddio_reg>;
|
||||
vcca-supply = <&vcca_reg>;
|
||||
vddio-supply = <&vddio_reg>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -51,25 +51,25 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-28nm-lp";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
reg-names = "dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-28nm-lp";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
reg-names = "dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vddio-supply = <&vddio_reg>;
|
||||
vddio-supply = <&vddio_reg>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
|
|
|
|||
|
|
@ -54,23 +54,23 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94900 0x260>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94900 0x260>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vdds-supply = <&vreg_l5a_0p88>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
vdds-supply = <&vreg_l5a_0p88>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -78,7 +78,6 @@ examples:
|
|||
"mdp1-mem",
|
||||
"cpu-cfg";
|
||||
|
||||
|
||||
resets = <&dispcc_core_bcr>;
|
||||
power-domains = <&dispcc_gdsc>;
|
||||
|
||||
|
|
@ -129,7 +128,7 @@ examples:
|
|||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf0_out: endpoint {
|
||||
remote-endpoint = <&mdss0_dp0_in>;
|
||||
remote-endpoint = <&mdss0_dp0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -168,7 +167,8 @@ examples:
|
|||
reg = <0xaf54000 0x104>,
|
||||
<0xaf54200 0x0c0>,
|
||||
<0xaf55000 0x770>,
|
||||
<0xaf56000 0x09c>;
|
||||
<0xaf56000 0x09c>,
|
||||
<0xaf57000 0x09c>;
|
||||
|
||||
interrupt-parent = <&mdss0>;
|
||||
interrupts = <12>;
|
||||
|
|
@ -208,8 +208,8 @@ examples:
|
|||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdss0_dp_out: endpoint { };
|
||||
reg = <1>;
|
||||
mdss0_dp_out: endpoint { };
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
108
dts/upstream/Bindings/display/msm/qcom,sm6150-dpu.yaml
Normal file
108
dts/upstream/Bindings/display/msm/qcom,sm6150-dpu.yaml
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM6150 Display DPU
|
||||
|
||||
maintainers:
|
||||
- Abhinav Kumar <quic_abhinavk@quicinc.com>
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6150-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display ahb clock
|
||||
- description: Display hf axi clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm6150-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc_mdss_ahb_clk>,
|
||||
<&gcc_disp_hf_axi_clk>,
|
||||
<&dispcc_mdss_mdp_clk>,
|
||||
<&dispcc_mdss_vsync_clk>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
assigned-clocks = <&dispcc_mdss_vsync_clk>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf0_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-19200000 {
|
||||
opp-hz = /bits/ 64 <19200000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-25600000 {
|
||||
opp-hz = /bits/ 64 <25600000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-307200000 {
|
||||
opp-hz = /bits/ 64 <307200000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
245
dts/upstream/Bindings/display/msm/qcom,sm6150-mdss.yaml
Normal file
245
dts/upstream/Bindings/display/msm/qcom,sm6150-mdss.yaml
Normal file
|
|
@ -0,0 +1,245 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM6150 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Abhinav Kumar <quic_abhinavk@quicinc.com>
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS are mentioned for SM6150 target.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm6150-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display hf axi clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
maxItems: 2
|
||||
|
||||
interconnect-names:
|
||||
maxItems: 2
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6150-dpu
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm6150-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6150-dsi-phy-14nm
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,icc.h>
|
||||
#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sm6150-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
|
||||
interconnect-names = "mdp0-mem", "cpu-cfg";
|
||||
|
||||
power-domains = <&dispcc_mdss_gdsc>;
|
||||
|
||||
clocks = <&dispcc_mdss_ahb_clk>,
|
||||
<&gcc_disp_hf_axi_clk>,
|
||||
<&dispcc_mdss_mdp_clk>;
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x0>;
|
||||
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm6150-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc_mdss_ahb_clk>,
|
||||
<&gcc_disp_hf_axi_clk>,
|
||||
<&dispcc_mdss_mdp_clk>,
|
||||
<&dispcc_mdss_vsync_clk>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
assigned-clocks = <&dispcc_mdss_vsync_clk>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf0_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-19200000 {
|
||||
opp-hz = /bits/ 64 <19200000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-25600000 {
|
||||
opp-hz = /bits/ 64 <25600000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-307200000 {
|
||||
opp-hz = /bits/ 64 <307200000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,sm6150-dsi-ctrl",
|
||||
"qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc_mdss_byte0_clk>,
|
||||
<&dispcc_mdss_byte0_intf_clk>,
|
||||
<&dispcc_mdss_pclk0_clk>,
|
||||
<&dispcc_mdss_esc0_clk>,
|
||||
<&dispcc_mdss_ahb_clk>,
|
||||
<&gcc_disp_hf_axi_clk>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
|
||||
<&dispcc_mdss_pclk0_clk_src>;
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi0_opp_table>;
|
||||
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdss_dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdss_dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-164000000 {
|
||||
opp-hz = /bits/ 64 <164000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi0_phy: phy@ae94400 {
|
||||
compatible = "qcom,sm6150-dsi-phy-14nm";
|
||||
reg = <0x0ae94400 0x100>,
|
||||
<0x0ae94500 0x300>,
|
||||
<0x0ae94800 0x188>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc_mdss_ahb_clk>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -42,6 +42,8 @@ properties:
|
|||
# Admatec 9904379 10.1" 1024x600 LVDS panel
|
||||
- admatec,9904379
|
||||
- auo,b101ew05
|
||||
# AUO G084SN05 V9 8.4" 800x600 LVDS panel
|
||||
- auo,g084sn05
|
||||
# Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel
|
||||
- chunghwa,claa070wp03xg
|
||||
# EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel
|
||||
|
|
|
|||
|
|
@ -206,12 +206,16 @@ properties:
|
|||
- mitsubishi,aa070mc01-ca1
|
||||
# Mitsubishi AA084XE01 8.4" XGA TFT LCD panel
|
||||
- mitsubishi,aa084xe01
|
||||
# Multi-Inno Technology Co.,Ltd MI0700A2T-30 7" 800x480 TFT Resistive Touch Module
|
||||
- multi-inno,mi0700a2t-30
|
||||
# Multi-Inno Technology Co.,Ltd MI0700S4T-6 7" 800x480 TFT Resistive Touch Module
|
||||
- multi-inno,mi0700s4t-6
|
||||
# Multi-Inno Technology Co.,Ltd MI0800FT-9 8" 800x600 TFT Resistive Touch Module
|
||||
- multi-inno,mi0800ft-9
|
||||
# Multi-Inno Technology Co.,Ltd MI1010AIT-1CP 10.1" 1280x800 LVDS IPS Cap Touch Mod.
|
||||
- multi-inno,mi1010ait-1cp
|
||||
# Multi-Inno Technology Co.,Ltd MI1010Z1T-1CP11 10.1" 1024x600 TFT Resistive Touch Module
|
||||
- multi-inno,mi1010z1t-1cp11
|
||||
# NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
|
||||
- nec,nl12880bc20-05
|
||||
# NEC LCD Technologies,Ltd. WQVGA TFT LCD panel
|
||||
|
|
@ -280,10 +284,14 @@ properties:
|
|||
- team-source-display,tst043015cmhx
|
||||
# Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
|
||||
- tianma,tm070jdhg30
|
||||
# Tianma Micro-electronics TM070JDHG34-00 7.0" WXGA (1280x800) LVDS TFT LCD panel
|
||||
- tianma,tm070jdhg34-00
|
||||
# Tianma Micro-electronics TM070JVHG33 7.0" WXGA TFT LCD panel
|
||||
- tianma,tm070jvhg33
|
||||
# Tianma Micro-electronics TM070RVHG71 7.0" WXGA TFT LCD panel
|
||||
- tianma,tm070rvhg71
|
||||
# Topland TIAN-G07017-01 7.0" WSVGA TFT-LCD panel with capacitive touch
|
||||
- topland,tian-g07017-01
|
||||
# Toshiba 8.9" WXGA (1280x768) TFT LCD panel
|
||||
- toshiba,lt089ac29000
|
||||
# TPK U.S.A. LLC Fusion 7" 800 x 480 (WVGA) LCD panel with capacitive touch
|
||||
|
|
|
|||
29
dts/upstream/Bindings/display/panel/powertip,hx8238a.yaml
Normal file
29
dts/upstream/Bindings/display/panel/powertip,hx8238a.yaml
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/powertip,hx8238a.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Powertip Electronic Technology Co. 320 x 240 LCD panel
|
||||
|
||||
maintainers:
|
||||
- Lukasz Majewski <lukma@denx.de>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-dpi.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: powertip,hx8238a
|
||||
- {} # panel-dpi, but not listed here to avoid false select
|
||||
|
||||
height-mm: true
|
||||
panel-timing: true
|
||||
port: true
|
||||
power-supply: true
|
||||
width-mm: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
...
|
||||
29
dts/upstream/Bindings/display/panel/powertip,st7272.yaml
Normal file
29
dts/upstream/Bindings/display/panel/powertip,st7272.yaml
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/powertip,st7272.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Powertip Electronic Technology Co. 320 x 240 LCD panel
|
||||
|
||||
maintainers:
|
||||
- Lukasz Majewski <lukma@denx.de>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-dpi.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: powertip,st7272
|
||||
- {} # panel-dpi, but not listed here to avoid false select
|
||||
|
||||
height-mm: true
|
||||
panel-timing: true
|
||||
port: true
|
||||
power-supply: true
|
||||
width-mm: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
...
|
||||
|
|
@ -23,6 +23,8 @@ properties:
|
|||
- samsung,atna45af01
|
||||
# Samsung 14.5" 3K (2944x1840 pixels) eDP AMOLED panel
|
||||
- samsung,atna45dc02
|
||||
# Samsung 15.6" 3K (2880x1620 pixels) eDP AMOLED panel
|
||||
- samsung,atna56ac03
|
||||
- const: samsung,atna33xc20
|
||||
|
||||
enable-gpios: true
|
||||
|
|
|
|||
|
|
@ -58,10 +58,10 @@ examples:
|
|||
#include <dt-bindings/power/r8a7796-sysc.h>
|
||||
|
||||
cmm0: cmm@fea40000 {
|
||||
compatible = "renesas,r8a7796-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0xfea40000 0x1000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 711>;
|
||||
resets = <&cpg 711>;
|
||||
compatible = "renesas,r8a7796-cmm",
|
||||
"renesas,rcar-gen3-cmm";
|
||||
reg = <0xfea40000 0x1000>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 711>;
|
||||
resets = <&cpg 711>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ properties:
|
|||
- renesas,du-r8a77995 # for R-Car D3 compatible DU
|
||||
- renesas,du-r8a779a0 # for R-Car V3U compatible DU
|
||||
- renesas,du-r8a779g0 # for R-Car V4H compatible DU
|
||||
- renesas,du-r8a779h0 # for R-Car V4M compatible DU
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -69,14 +70,12 @@ properties:
|
|||
$ref: /schemas/graph.yaml#/properties/port
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
renesas,cmms:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
maxItems: 1
|
||||
description:
|
||||
|
|
@ -85,6 +84,8 @@ properties:
|
|||
|
||||
renesas,vsps:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
items:
|
||||
- description: phandle to VSP instance that serves the DU channel
|
||||
|
|
@ -489,9 +490,11 @@ allOf:
|
|||
|
||||
renesas,cmms:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
|
||||
renesas,vsps:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
|
|
@ -558,9 +561,11 @@ allOf:
|
|||
|
||||
renesas,cmms:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
renesas,vsps:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
|
|
@ -627,9 +632,11 @@ allOf:
|
|||
|
||||
renesas,cmms:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
renesas,vsps:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
|
|
@ -683,7 +690,7 @@ allOf:
|
|||
- port@1
|
||||
|
||||
renesas,vsps:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
|
|
@ -746,9 +753,11 @@ allOf:
|
|||
|
||||
renesas,cmms:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
renesas,vsps:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
|
|
@ -799,6 +808,54 @@ allOf:
|
|||
|
||||
renesas,vsps:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
- renesas,vsps
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,du-r8a779h0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Functional clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: du.0
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: du.0
|
||||
|
||||
ports:
|
||||
properties:
|
||||
port@0:
|
||||
description: DSI 0
|
||||
port@1: false
|
||||
port@2: false
|
||||
port@3: false
|
||||
|
||||
required:
|
||||
- port@0
|
||||
|
||||
renesas,vsps:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- clock-names
|
||||
|
|
|
|||
|
|
@ -0,0 +1,120 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip specific extensions to the Synopsys Designware MIPI DSI2
|
||||
|
||||
maintainers:
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3588-mipi-dsi2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: sys
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
This SoC uses GRF regs to switch between vopl/vopb.
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: dcphy
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
const: apb
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Input node to receive pixel data.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DSI output node to panel.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- rockchip,grf
|
||||
- phys
|
||||
- phy-names
|
||||
- ports
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/display/dsi-controller.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/power/rk3588-power.h>
|
||||
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
dsi@fde20000 {
|
||||
compatible = "rockchip,rk3588-mipi-dsi2";
|
||||
reg = <0x0 0xfde20000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
|
||||
clock-names = "pclk", "sys";
|
||||
resets = <&cru SRST_P_DSIHOST0>;
|
||||
reset-names = "apb";
|
||||
power-domains = <&power RK3588_PD_VOP>;
|
||||
phys = <&mipidcphy0 PHY_TYPE_DPHY>;
|
||||
phy-names = "dcphy";
|
||||
rockchip,grf = <&vop_grf>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dsi0_in: port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
dsi0_out: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -23,7 +23,7 @@ properties:
|
|||
compatible:
|
||||
enum:
|
||||
- ti,am625-dss
|
||||
- ti,am62a7,dss
|
||||
- ti,am62a7-dss
|
||||
- ti,am65x-dss
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -100,12 +100,16 @@ properties:
|
|||
- description: Video layer, plane 1 (U/V or U)
|
||||
- description: Video layer, plane 2 (V)
|
||||
- description: Graphics layer
|
||||
- description: Audio channel 0
|
||||
- description: Audio channel 1
|
||||
dma-names:
|
||||
items:
|
||||
- const: vid0
|
||||
- const: vid1
|
||||
- const: vid2
|
||||
- const: gfx0
|
||||
- const: aud0
|
||||
- const: aud1
|
||||
|
||||
phys:
|
||||
description: PHYs for the DP data lanes
|
||||
|
|
@ -194,11 +198,13 @@ examples:
|
|||
power-domains = <&pd_dp>;
|
||||
resets = <&reset ZYNQMP_RESET_DP>;
|
||||
|
||||
dma-names = "vid0", "vid1", "vid2", "gfx0";
|
||||
dma-names = "vid0", "vid1", "vid2", "gfx0", "aud0", "aud1";
|
||||
dmas = <&xlnx_dpdma 0>,
|
||||
<&xlnx_dpdma 1>,
|
||||
<&xlnx_dpdma 2>,
|
||||
<&xlnx_dpdma 3>;
|
||||
<&xlnx_dpdma 3>,
|
||||
<&xlnx_dpdma 4>,
|
||||
<&xlnx_dpdma 5>;
|
||||
|
||||
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
|
||||
<&psgtr 0 PHY_TYPE_DP 1 3>;
|
||||
|
|
|
|||
|
|
@ -1,61 +0,0 @@
|
|||
Analog Devices AXI-DMAC DMA controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "adi,axi-dmac-1.00.a".
|
||||
- reg: Specification for the controllers memory mapped register map.
|
||||
- interrupts: Specification for the controllers interrupt.
|
||||
- clocks: Phandle and specifier to the controllers AXI interface clock
|
||||
- #dma-cells: Must be 1.
|
||||
|
||||
Required sub-nodes:
|
||||
- adi,channels: This sub-node must contain a sub-node for each DMA channel. For
|
||||
the channel sub-nodes the following bindings apply. They must match the
|
||||
configuration options of the peripheral as it was instantiated.
|
||||
|
||||
Required properties for adi,channels sub-node:
|
||||
- #size-cells: Must be 0
|
||||
- #address-cells: Must be 1
|
||||
|
||||
Required channel sub-node properties:
|
||||
- reg: Which channel this node refers to.
|
||||
- adi,source-bus-width,
|
||||
adi,destination-bus-width: Width of the source or destination bus in bits.
|
||||
- adi,source-bus-type,
|
||||
adi,destination-bus-type: Type of the source or destination bus. Must be one
|
||||
of the following:
|
||||
0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
|
||||
1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
|
||||
2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
|
||||
|
||||
Deprecated optional channel properties:
|
||||
- adi,length-width: Width of the DMA transfer length register.
|
||||
- adi,cyclic: Must be set if the channel supports hardware cyclic DMA
|
||||
transfers.
|
||||
- adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
|
||||
|
||||
DMA clients connected to the AXI-DMAC DMA controller must use the format
|
||||
described in the dma.txt file using a one-cell specifier. The value of the
|
||||
specifier refers to the DMA channel index.
|
||||
|
||||
Example:
|
||||
|
||||
dma: dma@7c420000 {
|
||||
compatible = "adi,axi-dmac-1.00.a";
|
||||
reg = <0x7c420000 0x10000>;
|
||||
interrupts = <0 57 0>;
|
||||
clocks = <&clkc 16>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
adi,channels {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
dma-channel@0 {
|
||||
reg = <0>;
|
||||
adi,source-bus-width = <32>;
|
||||
adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;
|
||||
adi,destination-bus-width = <64>;
|
||||
adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;
|
||||
};
|
||||
};
|
||||
};
|
||||
129
dts/upstream/Bindings/dma/adi,axi-dmac.yaml
Normal file
129
dts/upstream/Bindings/dma/adi,axi-dmac.yaml
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/adi,axi-dmac.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog Devices AXI-DMAC DMA controller
|
||||
|
||||
description: |
|
||||
FPGA-based DMA controller designed for use with high-speed converter hardware.
|
||||
|
||||
http://analogdevicesinc.github.io/hdl/library/axi_dmac/index.html
|
||||
|
||||
maintainers:
|
||||
- Nuno Sa <nuno.sa@analog.com>
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: adi,axi-dmac-1.00.a
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
"#dma-cells":
|
||||
const: 1
|
||||
|
||||
adi,channels:
|
||||
deprecated: true
|
||||
type: object
|
||||
description:
|
||||
This sub-node must contain a sub-node for each DMA channel. This node is
|
||||
only required for IP versions older than 4.3.a and should otherwise be
|
||||
omitted.
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
"#size-cells":
|
||||
const: 0
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^dma-channel@[0-9a-f]+$":
|
||||
type: object
|
||||
description:
|
||||
DMA channel properties based on HDL compile-time configuration.
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
adi,source-bus-width:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Width of the source bus in bits.
|
||||
enum: [8, 16, 32, 64, 128]
|
||||
|
||||
adi,destination-bus-width:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Width of the destination bus in bits.
|
||||
enum: [8, 16, 32, 64, 128]
|
||||
|
||||
adi,source-bus-type:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Type of the source bus.
|
||||
|
||||
0: Memory mapped AXI interface
|
||||
1: Streaming AXI interface
|
||||
2: FIFO interface
|
||||
enum: [0, 1, 2]
|
||||
|
||||
adi,destination-bus-type:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Type of the destination bus (see adi,source-bus-type).
|
||||
enum: [0, 1, 2]
|
||||
|
||||
adi,length-width:
|
||||
deprecated: true
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Width of the DMA transfer length register.
|
||||
|
||||
adi,cyclic:
|
||||
deprecated: true
|
||||
type: boolean
|
||||
description:
|
||||
Must be set if the channel supports hardware cyclic DMA transfers.
|
||||
|
||||
adi,2d:
|
||||
deprecated: true
|
||||
type: boolean
|
||||
description:
|
||||
Must be set if the channel supports hardware 2D DMA transfers.
|
||||
|
||||
required:
|
||||
- reg
|
||||
- adi,source-bus-width
|
||||
- adi,destination-bus-width
|
||||
- adi,source-bus-type
|
||||
- adi,destination-bus-type
|
||||
|
||||
required:
|
||||
- "#size-cells"
|
||||
- "#address-cells"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- "#dma-cells"
|
||||
|
||||
examples:
|
||||
- |
|
||||
dma-controller@7c420000 {
|
||||
compatible = "adi,axi-dmac-1.00.a";
|
||||
reg = <0x7c420000 0x10000>;
|
||||
interrupts = <0 57 0>;
|
||||
clocks = <&clkc 16>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
|
@ -22,7 +22,9 @@ properties:
|
|||
number.
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun4i-a10-dma
|
||||
enum:
|
||||
- allwinner,sun4i-a10-dma
|
||||
- allwinner,suniv-f1c100s-dma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
79
dts/upstream/Bindings/dma/atmel,sama5d4-dma.yaml
Normal file
79
dts/upstream/Bindings/dma/atmel,sama5d4-dma.yaml
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/atmel,sama5d4-dma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip AT91 Extensible Direct Memory Access Controller
|
||||
|
||||
maintainers:
|
||||
- Nicolas Ferre <nicolas.ferre@microchip.com>
|
||||
- Charan Pedumuru <charan.pedumuru@microchip.com>
|
||||
|
||||
description:
|
||||
The DMA Controller (XDMAC) is a AHB-protocol central direct memory access
|
||||
controller. It performs peripheral data transfer and memory move operations
|
||||
over one or two bus ports through the unidirectional communication
|
||||
channel. Each channel is fully programmable and provides both peripheral
|
||||
or memory-to-memory transfers. The channel features are configurable at
|
||||
implementation.
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- atmel,sama5d4-dma
|
||||
- microchip,sama7g5-dma
|
||||
- items:
|
||||
- enum:
|
||||
- microchip,sam9x60-dma
|
||||
- microchip,sam9x7-dma
|
||||
- const: atmel,sama5d4-dma
|
||||
|
||||
"#dma-cells":
|
||||
description: |
|
||||
Represents the number of integer cells in the `dmas` property of client
|
||||
devices. The single cell specifies the channel configuration register:
|
||||
- bit 13: SIF (Source Interface Identifier) for memory interface.
|
||||
- bit 14: DIF (Destination Interface Identifier) for peripheral interface.
|
||||
- bit 30-24: PERID (Peripheral Identifier).
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: dma_clk
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#dma-cells"
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
#include <dt-bindings/dma/at91.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
dma-controller@f0008000 {
|
||||
compatible = "atmel,sama5d4-dma";
|
||||
reg = <0xf0008000 0x1000>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#dma-cells = <1>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
|
||||
clock-names = "dma_clk";
|
||||
};
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
* Atmel Extensible Direct Memory Access Controller (XDMAC)
|
||||
|
||||
* XDMA Controller
|
||||
Required properties:
|
||||
- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or
|
||||
"microchip,sama7g5-dma" or
|
||||
"microchip,sam9x7-dma", "atmel,sama5d4-dma".
|
||||
- reg: Should contain DMA registers location and length.
|
||||
- interrupts: Should contain DMA interrupt.
|
||||
- #dma-cells: Must be <1>, used to represent the number of integer cells in
|
||||
the dmas property of client devices.
|
||||
- The 1st cell specifies the channel configuration register:
|
||||
- bit 13: SIF, source interface identifier, used to get the memory
|
||||
interface identifier,
|
||||
- bit 14: DIF, destination interface identifier, used to get the peripheral
|
||||
interface identifier,
|
||||
- bit 30-24: PERID, peripheral identifier.
|
||||
|
||||
Example:
|
||||
|
||||
dma1: dma-controller@f0004000 {
|
||||
compatible = "atmel,sama5d4-dma";
|
||||
reg = <0xf0004000 0x200>;
|
||||
interrupts = <50 4 0>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
* DMA clients
|
||||
DMA clients connected to the Atmel XDMA controller must use the format
|
||||
described in the dma.txt file, using a one-cell specifier for each channel.
|
||||
The two cells in order are:
|
||||
1. A phandle pointing to the DMA controller.
|
||||
2. Channel configuration register. Configurable fields are:
|
||||
- bit 13: SIF, source interface identifier, used to get the memory
|
||||
interface identifier,
|
||||
- bit 14: DIF, destination interface identifier, used to get the peripheral
|
||||
interface identifier,
|
||||
- bit 30-24: PERID, peripheral identifier.
|
||||
|
||||
Example:
|
||||
|
||||
i2c2: i2c@f8024000 {
|
||||
compatible = "atmel,at91sam9x5-i2c";
|
||||
reg = <0xf8024000 0x4000>;
|
||||
interrupts = <34 4 6>;
|
||||
dmas = <&dma1
|
||||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
|
||||
| AT91_XDMAC_DT_PERID(6))>,
|
||||
<&dma1
|
||||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
|
||||
| AT91_XDMAC_DT_PERID(7))>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
|
@ -26,9 +26,13 @@ properties:
|
|||
- fsl,imx93-edma3
|
||||
- fsl,imx93-edma4
|
||||
- fsl,imx95-edma5
|
||||
- nxp,s32g2-edma
|
||||
- items:
|
||||
- const: fsl,ls1028a-edma
|
||||
- const: fsl,vf610-edma
|
||||
- items:
|
||||
- const: nxp,s32g3-edma
|
||||
- const: nxp,s32g2-edma
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
|
|
@ -221,6 +225,36 @@ allOf:
|
|||
properties:
|
||||
power-domains: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: nxp,s32g2-edma
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: dmamux0
|
||||
- const: dmamux1
|
||||
interrupts:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: tx-0-15
|
||||
- const: tx-16-31
|
||||
- const: err
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
"#dma-cells":
|
||||
const: 2
|
||||
dma-channels:
|
||||
const: 32
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -13,9 +13,6 @@ description: |
|
|||
maintainers:
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
|
|
@ -29,7 +26,19 @@ properties:
|
|||
- const: nvidia,tegra186-adma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description:
|
||||
The 'page' region describes the address space of the page
|
||||
used for accessing the DMA channel registers. The 'global'
|
||||
region describes the address space of the global DMA registers.
|
||||
In the absence of the 'reg-names' property, there must be a
|
||||
single entry that covers the address space of the global DMA
|
||||
registers and the DMA channel registers.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
interrupts:
|
||||
description: |
|
||||
|
|
@ -63,6 +72,49 @@ required:
|
|||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra210-adma
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: Full address space range of DMA registers.
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra186-adma
|
||||
then:
|
||||
anyOf:
|
||||
- properties:
|
||||
reg:
|
||||
items:
|
||||
- description: Full address space range of DMA registers.
|
||||
- properties:
|
||||
reg:
|
||||
items:
|
||||
- description: Channel Page address space range of DMA registers.
|
||||
reg-names:
|
||||
items:
|
||||
- const: page
|
||||
- properties:
|
||||
reg:
|
||||
items:
|
||||
- description: Channel Page address space range of DMA registers.
|
||||
- description: Global Page address space range of DMA registers.
|
||||
reg-names:
|
||||
items:
|
||||
- const: page
|
||||
- const: global
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -25,7 +25,9 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- qcom,qcm2290-gpi-dma
|
||||
- qcom,qcs8300-gpi-dma
|
||||
- qcom,qdu1000-gpi-dma
|
||||
- qcom,sa8775p-gpi-dma
|
||||
- qcom,sar2130p-gpi-dma
|
||||
- qcom,sc7280-gpi-dma
|
||||
- qcom,sdx75-gpi-dma
|
||||
|
|
@ -35,10 +37,12 @@ properties:
|
|||
- qcom,sm8450-gpi-dma
|
||||
- qcom,sm8550-gpi-dma
|
||||
- qcom,sm8650-gpi-dma
|
||||
- qcom,sm8750-gpi-dma
|
||||
- qcom,x1e80100-gpi-dma
|
||||
- const: qcom,sm6350-gpi-dma
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs615-gpi-dma
|
||||
- qcom,sdm670-gpi-dma
|
||||
- qcom,sm6125-gpi-dma
|
||||
- qcom,sm8150-gpi-dma
|
||||
|
|
|
|||
|
|
@ -15,6 +15,16 @@ allOf:
|
|||
properties:
|
||||
"#dma-cells":
|
||||
const: 3
|
||||
description: |
|
||||
Each cell represents the following:
|
||||
1. The mux input number/line for the request
|
||||
2. Bitfield representing DMA channel configuration that is passed
|
||||
to the real DMA controller
|
||||
3. Bitfield representing device dependent DMA features passed to
|
||||
the real DMA controller
|
||||
|
||||
For bitfield definitions of cells 2 and 3, see the associated
|
||||
bindings doc for the actual DMA controller in st,stm32-dma.yaml.
|
||||
|
||||
compatible:
|
||||
const: st,stm32h7-dmamux
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ properties:
|
|||
- ti,am62a-dmss-bcdma-csirx
|
||||
- ti,am64-dmss-bcdma
|
||||
- ti,j721s2-dmss-bcdma-csi
|
||||
- ti,j722s-dmss-bcdma-csi
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
|
|
@ -196,7 +197,9 @@ allOf:
|
|||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,j721s2-dmss-bcdma-csi
|
||||
enum:
|
||||
- ti,j721s2-dmss-bcdma-csi
|
||||
- ti,j722s-dmss-bcdma-csi
|
||||
then:
|
||||
properties:
|
||||
ti,sci-rm-range-bchan: false
|
||||
|
|
|
|||
|
|
@ -162,14 +162,17 @@ Example::
|
|||
status = "okay";
|
||||
}
|
||||
|
||||
Indentation
|
||||
-----------
|
||||
Indentation and wrapping
|
||||
------------------------
|
||||
|
||||
1. Use indentation according to Documentation/process/coding-style.rst.
|
||||
1. Use indentation and wrap lines according to
|
||||
Documentation/process/coding-style.rst.
|
||||
2. Each entry in arrays with multiple cells, e.g. "reg" with two IO addresses,
|
||||
shall be enclosed in <>.
|
||||
3. For arrays spanning across lines, it is preferred to align the continued
|
||||
entries with opening < from the first line.
|
||||
3. For arrays spanning across lines, it is preferred to split on item boundary
|
||||
and align the continued entries with opening < from the first line.
|
||||
Usually avoid splitting individual items unless they significantly exceed
|
||||
line wrap limit.
|
||||
|
||||
Example::
|
||||
|
||||
|
|
@ -177,6 +180,9 @@ Example::
|
|||
compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
|
||||
reg = <0x0 0x0c271000 0x0 0x1000>,
|
||||
<0x0 0x0c222000 0x0 0x1000>;
|
||||
/* Lines exceeding coding style line wrap limit: */
|
||||
interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
|
||||
};
|
||||
|
||||
Organizing DTSI and DTS
|
||||
|
|
|
|||
|
|
@ -134,9 +134,14 @@ properties:
|
|||
- const: atmel,24c64
|
||||
- items:
|
||||
- enum:
|
||||
- giantec,gt24p128f
|
||||
- renesas,r1ex24128
|
||||
- samsung,s524ad0xd1
|
||||
- const: atmel,24c128
|
||||
- items:
|
||||
- enum:
|
||||
- puya,p24c256c
|
||||
- const: atmel,24c256
|
||||
- items:
|
||||
- const: microchip,24aa025e48
|
||||
- items:
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue