esd PCI405 updated.

board/esd/pci405/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	= $(BOARD).o flash.o
+OBJS	= $(BOARD).o flash.o cmd_pci405.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $^

board/esd/pci405/cmd_pci405.c

@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2002
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <405gp_pci.h>
+#include <cmd_bsp.h>
+
+#include "pci405.h"
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
+
+#if 0 /* test-only */
+#include "../common/fpga.c"
+void error_print(void)
+{
+	int i;
+	volatile unsigned char *ptr;
+	volatile unsigned long *ptr2;
+	
+	printf("\n 2nd SJA1000:\n");
+	ptr = 0xf0000100;
+	for (i=0; i<0x20; i++) {
+		printf("%02x ", *ptr++);
+	}
+
+	ptr2 = 0xf0400008;
+	printf("\nTimestamp = %x\n", *ptr2);
+	udelay(1000);
+	printf("Timestamp = %x\n", *ptr2);
+	udelay(1000);
+	printf("Timestamp = %x\n", *ptr2);
+
+#if 0 /* test-only */
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	printf("Resetting FPGA...\n");
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	do_loadpci(NULL, 0,0, NULL);
+#endif
+}
+
+void read_loop(void)
+{
+	int i;
+	volatile unsigned char *ptr;
+	volatile unsigned char val;
+	volatile unsigned long *ptr2;
+
+	printf("\nread loop on 1st sja1000...");
+	while (1) {
+		ptr = 0xf0000000;
+/*		printf("\n1st SJA1000:\n");*/
+		for (i=0; i<0x20; i++) {
+			i = i;
+			val = *ptr++;
+/*			printf("%02x ", val);*/
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+	}
+}
+#endif
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int *ptr = 0;
+	int count = 0;
+	int count2 = 0;
+	int status;
+	int i;
+	char addr[16];
+	char str[] = "\\|/-";
+	char *local_args[2];
+
+#if 0 /* test-only */
+	puts("\nStarting sja1000 test...");
+	{
+		int count;
+		volatile unsigned char *ptr;
+		volatile unsigned char val;
+		volatile unsigned char val2;
+
+#if 1 /* write test */
+		ptr = 0xf0000014;
+		for (i=1; i<11; i++)
+			*ptr++ = i;
+#endif
+		
+		count = 0;
+		while (1) {
+			count++;
+#if 0 /* write test */
+			ptr = 0xf0000014;
+			for (i=1; i<11; i++)
+				*ptr++ = i;
+#endif
+#if 1 /* read test */
+			ptr = 0xf0000014;
+			for (i=1; i<11; i++) {
+				val = *ptr++;
+#if 1
+				if (val != i) {
+					ptr = 0xf0000100;
+					val = *ptr; /* trigger las */
+
+					ptr = 0xf0000014;
+					val2 = *ptr;
+
+					printf("\nERROR: count=%d: soll=%x ist=%x -> staring read loop on 1st sja1000...\n",	count, i, val);
+
+					printf("soll=%x ist=%x -> staring read loop on 1st sja1000...\n", 1, val2);
+
+					return 0; /* test-only */
+					udelay(1000);
+					error_print();
+					read_loop();
+					return 0;
+				}
+#endif
+			}
+#endif
+
+			/* Abort if ctrl-c was pressed */
+			if (ctrlc()) {
+				puts("\nAbort\n");
+				return 0;
+			}
+
+			if (!(count % 100000)) {
+				printf(".");
+			}
+		}
+	}
+#endif
+	/*
+	 * Mark sync address
+	 */
+	ptr = 0;
+	*ptr = 0xffffffff;
+	puts("\nWaiting for image from pci host -");
+
+	/*
+	 * Wait for host to write the start address
+	 */
+	while (*ptr == 0xffffffff) {
+		count++;
+		if (!(count % 100)) {
+			count2++;
+			putc(0x08); /* backspace */
+			putc(str[count2 % 4]);
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+
+		udelay(1000);
+	}
+
+	if (*ptr == PCI_RECONFIG_MAGIC) {
+		/*
+		 * Save own pci configuration in PRAM
+		 */
+		memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN);
+		ptr = (unsigned int *)PCI_REGS_ADDR + 1;
+		for (i=0; i<0x40; i+=4) {
+			pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
+		}
+		ptr = (unsigned int *)PCI_REGS_ADDR;
+		*ptr = crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
+
+		printf("\nStoring PCI Configuration Regs...\n");
+	} else {
+		sprintf(addr, "%08x", *ptr);
+		
+		/*
+		 * Boot image
+		 */
+		printf("\nBooting image at addr 0x%s ...\n", addr);
+		setenv("loadaddr", addr);
+		
+		local_args[0] = argv[0];
+		local_args[1] = NULL;
+		status = do_bootm (cmdtp, 0, 1, local_args);
+	}
+
+	return 0;
+}
+
+#endif

board/esd/pci405/pci405.c

@@ -29,25 +29,15 @@
 #include <pci.h>
 #include <405gp_pci.h>
 
+#include "pci405.h"
+
+
 /* ------------------------------------------------------------------------- */
 
 #if 0
 #define FPGA_DEBUG
 #endif
 
-#define PCI_RECONFIG_MAGIC       0x07081967
-
-
-struct pci_config_regs {
-	unsigned short  command;
-	unsigned char   latency_timer;
-	unsigned char   int_line;
-	unsigned long   bar1;
-	unsigned long   bar2;
-	unsigned long   magic;
-};
-
-
 /* fpga configuration data - generated by bin2cc */
 const unsigned char fpgadata[] =
 {
@@ -114,6 +104,8 @@ int misc_init_r (void)
 	int index;
 	int i;
 	struct pci_config_regs *pci_regs;
+	unsigned int *ptr;
+	unsigned int *magic;
 
 	/*
 	 * On PCI-405 the environment is saved in eeprom!
@@ -170,33 +162,34 @@ int misc_init_r (void)
 	}
 	putc ('\n');
 
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Check if magic for pci reconfig is written
+	 */
+	magic = (unsigned int *)0x00000004;
+	if (*magic == PCI_RECONFIG_MAGIC) {
 		/*
 		 * Rewrite pci config regs (only after soft-reset with magic set)
 		 */
-	pci_regs = (struct pci_config_regs *)0x10;
+		ptr = (unsigned int *)PCI_REGS_ADDR;
-	if (pci_regs->magic == PCI_RECONFIG_MAGIC) {
+		if (crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
-		puts("PCI:   Found magic, rewriting config regs...\n");
+			puts("Restoring PCI Configurations Regs!\n");
-		pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND,
+			ptr = (unsigned int *)PCI_REGS_ADDR + 1;
-				      pci_regs->command);
+			for (i=0; i<0x40; i+=4) {
-		pci_write_config_byte(PCIDEVID_405GP, PCI_LATENCY_TIMER,
+				pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
-				      pci_regs->latency_timer);
-		pci_write_config_byte(PCIDEVID_405GP, PCI_INTERRUPT_LINE,
-				      pci_regs->int_line);
-		pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1,
-				       pci_regs->bar1);
-		pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2,
-				       pci_regs->bar2);
 			}
-	pci_regs->magic = 0; /* clear magic again */
+		}
+		mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
 		
-#if 0 /* test-only */
+		*magic = 0;      /* clear pci reconfig magic again */
-	pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &(pci_regs->command));
+	}
-	pci_read_config_byte(PCIDEVID_405GP, PCI_LATENCY_TIMER, &(pci_regs->latency_timer));
-	pci_read_config_byte(PCIDEVID_405GP, PCI_INTERRUPT_LINE, &(pci_regs->int_line));
-	pci_read_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, &(pci_regs->bar1));
-	pci_read_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, &(pci_regs->bar2));
-	pci_regs->magic = PCI_RECONFIG_MAGIC; /* set magic */
-#endif
 
 	free(dst);
 	return (0);
@@ -215,7 +208,7 @@ int checkboard (void)
 	puts ("Board: ");
 
 	if (i == -1) {
-		puts ("### No HW ID - assuming CPCI405");
+		puts ("### No HW ID - assuming PCI405");
 	} else {
 		puts (str);
 	}
@@ -238,7 +231,11 @@ long int initdram (int board_type)
 	printf("strap=%x\n", mfdcr(strap)); /* test-only */
 #endif
 
+#if 0 /* test-only: all PCI405 version must report 16mb */
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+#else
+	return (16*1024*1024);
+#endif
 }
 
 /* ------------------------------------------------------------------------- */

include/configs/PCI405.h

@@ -40,9 +40,13 @@
 #define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r() on init	*/
 
+#if 1 /* test-only */
 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
+#else
+#define CONFIG_SYS_CLK_FREQ     16000000 /* external frequency to pll   */
+#endif
 
-#define CONFIG_BAUDRATE		9600
+#define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #if 0
@@ -78,6 +82,7 @@
 				CFG_CMD_ELF	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_I2C	| \
+				CFG_CMD_BSP	| \
 				CFG_CMD_EEPROM  )
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -87,6 +92,8 @@
 
 #define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
+#define	CONFIG_PRAM		2048	/* reserve 2 MB "protected RAM"	*/ 
+
 /*
  * Miscellaneous configurable options
  */
@@ -128,7 +135,7 @@
 
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -149,7 +156,7 @@
 #define CFG_PCI_SUBSYS_DEVICEID 0x0407  /* PCI Device ID: PCI-405       */
 #define CFG_PCI_CLASSCODE       0x0280  /* PCI Class Code: Network/Other*/
 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1MS  0xff000001      /* 16MB, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 
 #if 0 /* test-only */
@@ -158,8 +165,8 @@
 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 #else
 #define CFG_PCI_PTM2LA  0xef600000      /* point to internal regs       */
-#define CFG_PCI_PTM2MS  0xef600001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2MS  0xffe00001      /* 2MB, enable                  */
-#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -269,6 +276,7 @@
 
 /* Memory Bank 2 (CAN0, 1) initialization                                       */
 #define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+//#define CFG_EBC_PB2AP           0x038056C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 #define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 3 (FPGA internal) initialization                                 */
@@ -319,19 +327,13 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#if 1 /* test-only */
 #define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
-
 #define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
-#else
-#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM                   */
-#endif
 #define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 
-
 /*
  * Internal Definitions
  *