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riscv: Introduce configuration for 64bit version Microblaze V
The commit 7576ab2fac ("riscv: Add support for AMD/Xilinx MicroBlaze V")
added support for 32bit version. 64bit version is also available that's why
wire it up too.
DT is providing description for generic QEMU target.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Michal Simek
Leo Yu-Chi Liang
parent
e4b8d8be4e
commit
d5f5e77818
4 changed files with 192 additions and 0 deletions
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@ -10,6 +10,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
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dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
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dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
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dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
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dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
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dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
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dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
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dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
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dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb
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dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb
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include $(srctree)/scripts/Makefile.dts
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include $(srctree)/scripts/Makefile.dts
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99
arch/riscv/dts/xilinx-mbv64.dts
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99
arch/riscv/dts/xilinx-mbv64.dts
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@ -0,0 +1,99 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for AMD MicroBlaze V
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*
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* (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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#include "binman.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "AMD MicroBlaze V 64bit";
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compatible = "qemu,mbv", "amd,mbv";
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <100000000>;
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cpu_0: cpu@0 {
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compatible = "amd,mbv64", "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv64imafdc";
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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clock-frequency = <100000000>;
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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};
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aliases {
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serial0 = &uart0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0 0x40000000>;
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};
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clk100: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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axi: axi {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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bootph-all;
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axi_intc: interrupt-controller@41200000 {
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compatible = "xlnx,xps-intc-1.00.a";
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reg = <0 0x41200000 0 0x1000>;
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interrupt-controller;
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interrupt-parent = <&cpu0_intc>;
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#interrupt-cells = <2>;
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kind-of-intr = <0>;
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};
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xlnx_timer0: timer@41c00000 {
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compatible = "xlnx,xps-timer-1.00.a";
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reg = <0 0x41c00000 0 0x1000>;
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interrupt-parent = <&axi_intc>;
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interrupts = <0 2>;
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bootph-all;
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xlnx,one-timer-only = <0>;
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clock-names = "s_axi_aclk";
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clocks = <&clk100>;
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};
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uart0: serial@40600000 {
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compatible = "xlnx,xps-uartlite-1.00.a";
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reg = <0 0x40600000 0 0x1000>;
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interrupt-parent = <&axi_intc>;
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interrupts = <1 2>;
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bootph-all;
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clocks = <&clk100>;
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current-speed = <115200>;
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xlnx,data-bits = <8>;
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xlnx,use-parity = <0>;
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};
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};
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};
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44
configs/xilinx_mbv64_defconfig
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44
configs/xilinx_mbv64_defconfig
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@ -0,0 +1,44 @@
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CONFIG_RISCV=y
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CONFIG_SYS_MALLOC_LEN=0xe00000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
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CONFIG_ENV_SIZE=0x20000
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CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64"
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CONFIG_SPL_STACK=0x80200000
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CONFIG_SPL_BSS_START_ADDR=0x84000000
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CONFIG_SPL_BSS_MAX_SIZE=0x80000
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CONFIG_SYS_LOAD_ADDR=0x80200000
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CONFIG_SPL_SIZE_LIMIT=0x40000
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CONFIG_SPL=y
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CONFIG_DEBUG_UART_BASE=0x40600000
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CONFIG_DEBUG_UART_CLOCK=100000000
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CONFIG_SYS_CLK_FREQ=100000000
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CONFIG_BOOT_SCRIPT_OFFSET=0x0
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CONFIG_DEBUG_UART=y
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CONFIG_TARGET_XILINX_MBV=y
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CONFIG_ARCH_RV64I=y
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# CONFIG_SPL_SMP is not set
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CONFIG_REMAKE_ELF=y
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CONFIG_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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# CONFIG_BOARD_LATE_INIT is not set
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CONFIG_SPL_MAX_SIZE=0x40000
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_SYS_MALLOC=y
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CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
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# CONFIG_CMD_MII is not set
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CONFIG_CMD_TIMER=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DM_MTD=y
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_DEBUG_UART_SKIP_INIT=y
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CONFIG_XILINX_UARTLITE=y
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CONFIG_XILINX_TIMER=y
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# CONFIG_BINMAN_FDT is not set
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CONFIG_PANIC_HANG=y
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CONFIG_SPL_GZIP=y
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48
configs/xilinx_mbv64_smode_defconfig
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48
configs/xilinx_mbv64_smode_defconfig
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CONFIG_RISCV=y
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CONFIG_SYS_MALLOC_LEN=0xe00000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
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CONFIG_ENV_SIZE=0x20000
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CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64"
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CONFIG_SPL_STACK=0x80200000
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CONFIG_SPL_BSS_START_ADDR=0x84000000
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CONFIG_SPL_BSS_MAX_SIZE=0x80000
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CONFIG_SYS_LOAD_ADDR=0x80200000
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CONFIG_SPL_SIZE_LIMIT=0x40000
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CONFIG_SPL=y
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CONFIG_DEBUG_UART_BASE=0x40600000
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CONFIG_DEBUG_UART_CLOCK=1000000
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CONFIG_SYS_CLK_FREQ=100000000
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CONFIG_BOOT_SCRIPT_OFFSET=0x0
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CONFIG_TARGET_XILINX_MBV=y
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CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80100000
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CONFIG_ARCH_RV64I=y
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CONFIG_RISCV_SMODE=y
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# CONFIG_SPL_SMP is not set
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CONFIG_REMAKE_ELF=y
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CONFIG_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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# CONFIG_BOARD_LATE_INIT is not set
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CONFIG_SPL_MAX_SIZE=0x40000
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_SYS_MALLOC=y
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CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
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CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
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# CONFIG_CMD_MII is not set
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CONFIG_CMD_TIMER=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DM_MTD=y
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CONFIG_DEBUG_UART_UARTLITE=y
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_DEBUG_UART_SKIP_INIT=y
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CONFIG_XILINX_UARTLITE=y
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# CONFIG_RISCV_TIMER is not set
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CONFIG_XILINX_TIMER=y
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# CONFIG_BINMAN_FDT is not set
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CONFIG_PANIC_HANG=y
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CONFIG_SPL_GZIP=y
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