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video: tegra20: consolidate DC header
Consolidate HD headers and place the result into video/tegra20 since it is used only by devices from this directory. Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 Tested-by: Ion Agorria <ion@agorria.com> # HTC One X Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Svyatoslav Ryhel
Anatolij Gustschin
parent
dc43aa6a79
commit
d5e1eaf97e
8 changed files with 46 additions and 95 deletions
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@ -569,12 +569,4 @@ enum {
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#define DC_N_WINDOWS 5
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#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
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#define TEGRA_DSI_A "dsi@54300000"
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#define TEGRA_DSI_B "dsi@54400000"
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struct tegra_dc_plat {
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struct udevice *dev; /* Display controller device */
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struct dc_ctlr *dc; /* Display controller regmap */
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};
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#endif /* __ASM_ARCH_TEGRA_DC_H */
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@ -1,28 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
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#define __ASM_ARCH_TEGRA_DISPLAY_H
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#include <asm/arch-tegra/dc.h>
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/* This holds information about a window which can be displayed */
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struct disp_ctl_win {
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enum win_color_depth_id fmt; /* Color depth/format */
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unsigned int bpp; /* Bits per pixel */
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phys_addr_t phys_addr; /* Physical address in memory */
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unsigned int x; /* Horizontal address offset (bytes) */
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unsigned int y; /* Veritical address offset (bytes) */
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unsigned int w; /* Width of source window */
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unsigned int h; /* Height of source window */
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unsigned int stride; /* Number of bytes per line */
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unsigned int out_x; /* Left edge of output window (col) */
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unsigned int out_y; /* Top edge of output window (row) */
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unsigned int out_w; /* Width of output window in pixels */
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unsigned int out_h; /* Height of output window in pixels */
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};
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#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
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@ -1,28 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
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#define __ASM_ARCH_TEGRA_DISPLAY_H
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#include <asm/arch-tegra/dc.h>
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/* This holds information about a window which can be displayed */
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struct disp_ctl_win {
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enum win_color_depth_id fmt; /* Color depth/format */
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unsigned bpp; /* Bits per pixel */
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phys_addr_t phys_addr; /* Physical address in memory */
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unsigned x; /* Horizontal address offset (bytes) */
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unsigned y; /* Veritical address offset (bytes) */
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unsigned w; /* Width of source window */
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unsigned h; /* Height of source window */
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unsigned stride; /* Number of bytes per line */
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unsigned out_x; /* Left edge of output window (col) */
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unsigned out_y; /* Top edge of output window (row) */
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unsigned out_w; /* Width of output window in pixels */
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unsigned out_h; /* Height of output window in pixels */
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};
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#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
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@ -1,28 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
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#define __ASM_ARCH_TEGRA_DISPLAY_H
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#include <asm/arch-tegra/dc.h>
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/* This holds information about a window which can be displayed */
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struct disp_ctl_win {
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enum win_color_depth_id fmt; /* Color depth/format */
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unsigned int bpp; /* Bits per pixel */
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phys_addr_t phys_addr; /* Physical address in memory */
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unsigned int x; /* Horizontal address offset (bytes) */
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unsigned int y; /* Veritical address offset (bytes) */
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unsigned int w; /* Width of source window */
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unsigned int h; /* Height of source window */
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unsigned int stride; /* Number of bytes per line */
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unsigned int out_x; /* Left edge of output window (col) */
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unsigned int out_y; /* Top edge of output window (row) */
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unsigned int out_w; /* Width of output window in pixels */
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unsigned int out_h; /* Height of output window in pixels */
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};
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#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
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@ -21,7 +21,8 @@
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/pwm.h>
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#include <asm/arch/display.h>
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#include "tegra-dc.h"
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DECLARE_GLOBAL_DATA_PTR;
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41
drivers/video/tegra20/tegra-dc.h
Normal file
41
drivers/video/tegra20/tegra-dc.h
Normal file
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@ -0,0 +1,41 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _TEGRA_DC_H
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#define _TEGRA_DC_H
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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/* arch-tegra/dc exists only because T124 uses it */
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#include <asm/arch-tegra/dc.h>
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#define TEGRA_DSI_A "dsi@54300000"
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#define TEGRA_DSI_B "dsi@54400000"
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struct tegra_dc_plat {
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struct udevice *dev; /* Display controller device */
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struct dc_ctlr *dc; /* Display controller regmap */
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};
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/* This holds information about a window which can be displayed */
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struct disp_ctl_win {
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enum win_color_depth_id fmt; /* Color depth/format */
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unsigned int bpp; /* Bits per pixel */
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phys_addr_t phys_addr; /* Physical address in memory */
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unsigned int x; /* Horizontal address offset (bytes) */
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unsigned int y; /* Veritical address offset (bytes) */
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unsigned int w; /* Width of source window */
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unsigned int h; /* Height of source window */
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unsigned int stride; /* Number of bytes per line */
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unsigned int out_x; /* Left edge of output window (col) */
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unsigned int out_y; /* Top edge of output window (row) */
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unsigned int out_w; /* Width of output window in pixels */
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unsigned int out_h; /* Height of output window in pixels */
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};
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#endif /* _TEGRA_DC_H */
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@ -20,9 +20,9 @@
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/display.h>
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#include <asm/arch-tegra30/dsi.h>
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#include "tegra-dc.h"
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#include "mipi-phy.h"
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struct tegra_dsi_priv {
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@ -15,7 +15,8 @@
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/display.h>
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#include "tegra-dc.h"
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#define TEGRA_DISPLAY_A_BASE 0x54200000
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#define TEGRA_DISPLAY_B_BASE 0x54240000
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