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arm: dts: rzg2l: Sync with Linux v6.7

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Pull in the recent changes to the RZ/G2L device tree and related dtsi
files so that we're aligned with Linux v6.7 (commit 0dd3ee311255).

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Paul Barker 2024-02-27 20:40:29 +00:00 • committed by Marek Vasut
parent aecd69879d
commit d4f0ff93c8
6 changed files with 118 additions and 22 deletions
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16
arch/arm/dts/r9a07g044.dtsi
View file

@ -223,20 +223,20 @@
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tgiv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tgiv1", "tgiu1",
"tgia2", "tgib2", "tgiv2", "tgiu2",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
"tgia2", "tgib2", "tciv2", "tciu2",
"tgia3", "tgib3", "tgic3", "tgid3",
"tgiv3",
"tciv3",
"tgia4", "tgib4", "tgic4", "tgid4",
"tgiv4",
"tciv4",
"tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6",
"tgiv6",
"tciv6",
"tgia7", "tgib7", "tgic7", "tgid7",
"tgiv7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
"tgiv8", "tgiu8";
"tciv8", "tciu8";
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;

21
arch/arm/dts/r9a07g044l2-smarc.dts
View file

@ -6,6 +6,27 @@
*/
/dts-v1/;
/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
#define PMOD1_SER0 1
/*
* To enable MTU3a PWM on PMOD0,
* Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
* enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
*/
#define PMOD_MTU3 0
#if (PMOD_MTU3 && PMOD1_SER0)
#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
#endif
#define MTU3_COUNTER_Z_PHASE_SIGNAL 0
#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
#endif
#include "r9a07g044l2.dtsi"
#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc-pinfunction.dtsi"

18
arch/arm/dts/rz-smarc-common.dtsi
View file

@ -32,12 +32,6 @@
stdout-path = "serial0:115200n8";
};
audio_mclock: audio_mclock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
snd_rzg2l: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@ -55,7 +49,7 @@
};
codec_dai: simple-audio-card,codec {
clocks = <&audio_mclock>;
clocks = <&versa3 2>;
sound-dai = <&wm8978>;
};
};
@ -76,13 +70,19 @@
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
x1: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&audio_clk1{
&audio_clk1 {
clock-frequency = <11289600>;
};
&audio_clk2{
&audio_clk2 {
clock-frequency = <12288000>;
};

20
arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
View file

@ -53,6 +53,26 @@
<RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
};
mtu3_pins: mtu3 {
mtu3-ext-clk-input-pin {
pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
<RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */
};
mtu3-pwm {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
<RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
<RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
<RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
};
#if MTU3_COUNTER_Z_PHASE_SIGNAL
mtu3-zphase-clk {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */
};
#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
};
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */

22
arch/arm/dts/rzg2l-smarc-som.dtsi
View file

@ -73,6 +73,13 @@
gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
regulator-always-on;
};
/* 32.768kHz crystal */
x2: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&adc {
@ -100,7 +107,7 @@
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
@ -128,7 +135,7 @@
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
@ -148,6 +155,17 @@
mali-supply = <&reg_1p1v>;
};
&i2c3 {
raa215300: pmic@12 {
compatible = "renesas,raa215300";
reg = <0x12>, <0x6f>;
reg-names = "main", "rtc";
clocks = <&x2>;
clock-names = "xin";
};
};
&ostm1 {
status = "okay";
};

43
arch/arm/dts/rzg2l-smarc.dtsi
View file

@ -8,9 +8,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
#define PMOD1_SER0 1
/ {
aliases {
serial1 = &scif2;
@ -113,8 +110,48 @@
#sound-dai-cells = <0>;
reg = <0x1a>;
};
versa3: clock-generator@68 {
compatible = "renesas,5p35023";
reg = <0x68>;
#clock-cells = <1>;
clocks = <&x1>;
renesas,settings = [
80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
80 b0 45 c4 95
];
assigned-clocks = <&versa3 0>, <&versa3 1>,
<&versa3 2>, <&versa3 3>,
<&versa3 4>, <&versa3 5>;
assigned-clock-rates = <24000000>, <11289600>,
<11289600>, <12000000>,
<25000000>, <12288000>;
};
};
#if PMOD_MTU3
&mtu3 {
pinctrl-0 = <&mtu3_pins>;
pinctrl-names = "default";
status = "okay";
};
#if MTU3_COUNTER_Z_PHASE_SIGNAL
/* SDHI cd pin is muxed with counter Z phase signal */
&sdhi1 {
status = "disabled";
};
#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
&spi1 {
status = "disabled";
};
#endif /* PMOD_MTU3 */
/*
* To enable SCIF2 (SER0) on PMOD1 (CN7)
* SW1 should be at position 2->3 so that SER0_CTS# line is activated